The Community for Technology Leaders
Computer-Aided Design, International Conference on (2005)
San Jose, CA, USA
May 31, 2005 to May 31, 2005
ISBN: 0-7803-9254-X
TABLE OF CONTENTS
Introduction

Title Page (PDF)

pp. 0

Table of contents (PDF)

pp. xix-xxx
Session 1A - Memory and arithmetic optimizations

Storage assignment during high-level synthesis for configurable architectures (Abstract)

Gang Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Wenrui Gong , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
R. Kastner , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 3-6

Performance-driven read-after-write dependencies softening in high-level synthesis (Abstract)

M.C. Molina , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
R. Ruiz-Sautua , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
R. Hermida , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
J.M. Mendias , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 7-12

An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications (Abstract)

J. Monteiro , IST-INESC-ID, Lisboa, Portugal
E. Costa , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
P. Flores , IST-INESC-ID, Lisboa, Portugal
pp. 13-16
Session 1B - Design manufacturing interaction

FPGA device and architecture evaluation considering process variations (Abstract)

Lerong Cheng , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Ho-Yan Wong , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Lei He , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Yan Lin , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 19-24

Via-configurable routing architectures and fast design mappability estimation for regular fabrics (Abstract)

Y. Ran , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 25-32
Session 1C - Detailed placement

Computational geometry based placement migration (Abstract)

D.Z. Pan , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
H. Ren , Dept. of ECE, Texas Univ. at Austin, TX, USA
T. Luo , Dept. of ECE, Texas Univ. at Austin, TX, USA
C.J. Alpert , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 41-47

An efficient and effective detailed placement algorithm (Abstract)

C. Chu , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
N. Viswanathan , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Min Pan , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 48-55

Post-placement rewiring and rebuffering by exhaustive search for functional symmetries (Abstract)

V. Bertacco , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
I.L. Markov , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Kai-hui Chang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 56-63

Wirelength optimization by optimal block orientation (Abstract)

F. Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Xin Hao , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 64-70
Session 1D - Digital, analog and RF test

Response shaper: a novel technique to enhance unknown tolerance for output response compaction (Abstract)

Seongmoon Wang , Duke Univ., Durham, NC, USA
Kwang-Ting Cheng , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
S.T. Chakradhar , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
M.C.-T. Chao , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, Santa Barbara, CA, USA
pp. 80-87

Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs (Abstract)

A. Sehgal , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 88-93

A cocktail approach on random access scan toward low power and high efficiency test (Abstract)

K. Chakrabarty , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin Chu, Taiwan
K. Chakrabarty , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin Chu, Taiwan
J.E. Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin Chu, Taiwan
pp. 94-99

A statistical study of the effectiveness of BIST jitter measurement techniques (Abstract)

M. Soma , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
H. Nguyen , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
D. Bordoley , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 100-107
Session 2A - Embedded turorial: design trends

The circuit design of the synergistic processor element of a CELL processor (Abstract)

B. Flachs , IBM Syst. & Technol. Group, Austin, TX, USA
S.H. Dhong , IBM Syst. & Technol. Group, Austin, TX, USA
R. Cook , IBM Syst. & Technol. Group, Austin, TX, USA
S. Cottier , IBM Syst. & Technol. Group, Austin, TX, USA
O. Takahashi , IBM Syst. & Technol. Group, Austin, TX, USA
pp. 111-117

Adaptive designs for power and thermal optimization (Abstract)

R. McGowen , Intel Corp., Fort Collins, CO, USA
pp. 118-121

Digital RF processor (DRP/spl trade/) for cellular phones (Abstract)

K. Muhammad , Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX, USA
D. Leipold , Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX, USA
R.B. Staszewski , Wireless Analog Technol. Center, Texas Instruments Inc., Dallas, TX, USA
pp. 122-129
Session 2B - Physical design for manufacturing

A layout dependent full-chip copper electroplating topography model (Abstract)

Jianfeng Luo , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
J. Kawa , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
Qing Su , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
C. Chiang , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
pp. 133-140

Interval-valued statistical modeling of oxide chemical-mechanical polishing (Abstract)

C.F. Fang , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
J.D. Ma , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
Xiaolin Xie , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
D.S. Boning , IBM Syst. & Technol. Group, Austin, TX, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
pp. 141-148

Fast and efficient phase conflict detection and correction in standard-cell layouts (Abstract)

X. Xu , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
A.B. Kahng , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
S. Sinha , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., New York, NY, USA
C. Chiang , Adv. Technol. Group, Synopsys, Mountain View, CA, USA
pp. 149-156
Session 2C - Large-scale layout techniques

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs (Abstract)

Shyh-Chang Lin , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
Yao-Wen Chang , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
Tung-Chieh Chen , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
pp. 159-164

Robust mixed-size placement under tight white-space constraints (Abstract)

J.R. Shinnerl , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
M. Romesis , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
J. Cong , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
pp. 165-172

Intrinsic shortest path length: a new, accurate a priori wirelength estimator (Abstract)

A.B. Kahng , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
S. Reda , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 173-180
Session 2D - Novel ideas and logic synthesis

Synthesis methodology for built-in at-speed testing (Abstract)

Yinghua Li , California Univ., Berkeley, CA, USA
R. Brayton , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
A. Kondratyev , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 183-188

Clustering for processing rate optimization (Abstract)

Hai Zhou , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Chuan Lin , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Jia Wang , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 189-195

ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing (Abstract)

Weijen Chen , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
Weijen Chen , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
Sanghamitra Roy , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
pp. 196-203
Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices

FinFETs for nanoscale CMOS digital integrated circuits (Abstract)

Tsu-Jae King , Adv. Technol. Group, Synopsys, Inc., Mountain View, CA, USA
pp. 207-210

Physics-based compact modeling for nonclassical CMOS (Abstract)

V.P. Trivedi , Freescale Semicond., Austin, TX, USA
W. Zhang , IBM Syst. & Technol. Group, Austin, TX, USA
M.M. Chowdhury , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
L. Mathew , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
G. Fossum , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
pp. 211-216

Double-gate SOI devices for low-power and high-performance applications (Abstract)

K. Roy , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
S. Mukhopadhyay , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
H. Mahmoodi , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
H. Ananthan , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
A. Bansal , IBM Syst. & Technol. Group, Austin, TX, USA
pp. 217-224

Thermal simulation techniques for nanoscale transistors (Abstract)

S. Sinha , Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
M. Panzer , Adv. Technol. Group, Synopsys Inc., Mountain View, CA, USA
J. Rowlette , Dept. of Electr. & Mech. Eng., Stanford Univ., CA, USA
K. Goodson , IBM Syst. & Technol. Group, Austin, TX, USA
E. Pop , Dept. of Electr. & Mech. Eng., Stanford Univ., CA, USA
pp. 225-228
Session 3B - Routing and application specific NoC architectures

An automated technique for topology and route generation of application specific on-chip interconnection networks (Abstract)

K.S. Chatha , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
G. Konjevod , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
K. Srinivasan , Dept. of CSE, Arizona State Univ., Tempe, AZ, USA
pp. 231-237

Deadlock-free routing and component placement for irregular mesh-based networks-on-chip (Abstract)

H. Zimmer , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
T. Hollstein , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M.K.F. Schafer , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 238-245

Application-specific network-on-chip architecture customization via long-range link insertion (Abstract)

U.Y. Ogras , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 246-253

NoCEE: energy macro-model extraction methodology for network on chip routers (Abstract)

J. Chan , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
S. Parameswaran , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 254-259
Session 3C - Memory driven code and architecture optimizations

Architecture and compilation for data bandwidth improvement in configurable embedded processors (Abstract)

J. Cong , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
Guoling Han , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
Zhiru Zhang , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
pp. 263-270

Code restructuring for improving cache performance of MPSoCs (Abstract)

G. Chen , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA
pp. 271-274

2D data locality: definition, abstraction, and application (Abstract)

M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 275-278

Integrating loop and data optimizations for locality within a constraint network based framework (Abstract)

Guilin Chen , Pennsylvania State Univ., University Park, PA, USA
O. Ozturk , Pennsylvania State Univ., University Park, PA, USA
I. Kolcu , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Kandemir , Pennsylvania State Univ., University Park, PA, USA
pp. 279-282
Session 3D - Exploiting arithmetic constructs in verification

System level verification of digital signal processing applications based on the polynomial abstraction technique (Abstract)

A.K. Singh , R. Inst. of Technol., Stockholm, Sweden
A. Jantsch , R. Inst. of Technol., Stockholm, Sweden
T. Raudvere , R. Inst. of Technol., Stockholm, Sweden
I. Sander , R. Inst. of Technol., Stockholm, Sweden
pp. 285-290

Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra (Abstract)

F. Enescu , R. Inst. of Technol., Stockholm, Sweden
N. Shekhar , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake, UT, USA
P. Kalla , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake, UT, USA
S. Gopalakrishnan , R. Inst. of Technol., Stockholm, Sweden
pp. 291-296

RTL SAT simplification by Boolean and interval arithmetic reasoning (Abstract)

M.K. Iyer , California Univ., Santa Barbara, CA, USA
F. Brewer , California Univ., Santa Barbara, CA, USA
K.-T. Cheng , California Univ., Santa Barbara, CA, USA
G. Parthasarathy , California Univ., Santa Barbara, CA, USA
pp. 297-302

Runtime integrity checking for inter-object connections (Abstract)

Guilin Chen , Pennsylvania State Univ., University Park, PA, USA
Mahmut Kandemir , Pennsylvania State Univ., University Park, PA, USA
pp. 303-306
Session 4A - Buffers and voltage islands

Post-placement voltage island generation under performance requirement (Abstract)

I-Min Liu , Pennsylvania State Univ., University Park, PA, USA
M.D.F. Wong , California Univ., Santa Barbara, CA, USA
Huaizhi Wu , Cadence Design Syst., Inc., San Jose, CA, USA
Yusu Wang , California Univ., Santa Barbara, CA, USA
pp. 309-316

Buffer insertion under process variations for delay minimization (Abstract)

M.D.F. Wong , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Liang Deng , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 317-321

Efficient algorithms for buffer insertion in general circuits based on network flow (Abstract)

Ruiming Chen , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 322-326
Session 4B - Sequential circuit optimization

Trade-off between latch and flop for min-period sequential circuit designs with crosstalk (Abstract)

Hai Zhou , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Chuan Lin , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 329-334

Flip-flop insertion with shifted-phase clocks for FPGA power reduction (Abstract)

Kyungsoo Lee , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Hyeonmin Lim , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Naehyuck Chang , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Youngjin Cho , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 335-342

Acyclic modeling of combinational loops (Abstract)

A. Gupta , Tabula, Inc., Santa Clara, CA, USA
C. Selvidge , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 343-347
Session 4C - Power grid verification

Fast algorithms for IR drop analysis in large power grid (Abstract)

Yu Zhong , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
M.D.F. Wong , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 351-357

Incremental partitioning-based vectorless power grid verification (Abstract)

D. Kouroussis , Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
I.A. Ferzli , Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
F.N. Najm , Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
pp. 358-364

Static timing analysis considering power supply variations (Abstract)

Sanjay Pant , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 365-371
Session 4D - Nanoelectronics

Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation (Abstract)

K.K. Likharev , Michigan Univ., Ann Arbor, MI, USA
A. DeHon , Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
pp. 375-382

Performance analysis of carbon nanotube interconnects for VLSI applications (Abstract)

K. Banerjee , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
N. Srivastava , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 383-390
Session 5A - Variability in design

DiCER: distributed and cost-effective redundancy for variation tolerance (Abstract)

Di Wu , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Quiyang Li , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
R. Mahapatra , IBM Syst. & Technol. Group, Austin, TX, USA
Jiang Hu , Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
G. Venkataraman , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 393-397

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability (Abstract)

K. Nii , Renesas Technol. Corp., Itami, Japan
S. Ohbayashi , IBM Syst. & Technol. Group, Austin, TX, USA
Y. Oda , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
Y. Tsukamoto , Renesas Technol. Corp., Itami, Japan
S. Imaoka , Dept. of Electr. & Comput. Eng.,, Toronto Univ., Ont., Canada
pp. 398-405

Noise margin analysis for dynamic logic circuits (Abstract)

M. Greenstreet , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
Suwen Yang , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 406-412
Session 5B - Efficient analog design space exploration techniques

Efficient analog platform characterization through analog constraint graphs (Abstract)

F. De Bernardinis , Dept. of Electr. Eng., California Comput. Sci. Univ., Berkeley, CA, USA
A. Sangiovanni Vincentelli , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 415-421

Performance-centering optimization for system-level analog design exploration (Abstract)

Jian Wang , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Xin Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Wanju Chiang , IBM Syst. & Technol. Group, Austin, TX, USA
Tun-Shih Chen , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
pp. 422-429

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits (Abstract)

R. Vemuri , Dept. of ECECS, Cincinnati Univ., OH, USA
A. Agarwal , Dept. of ECECS, Cincinnati Univ., OH, USA
pp. 430-436
Session 5C - Dynamic voltage scaling

Battery optimization vs energy optimization: which to choose and when? (Abstract)

R. Rao , NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
S. Vrudhula , NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
pp. 439-445

Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems (Abstract)

B. Mochocki , NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
R. Racu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Ernst , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
B. Mochocki , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 446-449

Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications (Abstract)

Jaewon Seo , KAIST, Daejeon, South Korea
Taewhan Kim , NSF Center for Low Power Electron., Arizona State Univ., Tempe, AZ, USA
N.D. Dutt , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 450-455

Compiler-directed voltage scaling on communication links for reducing power consumption (Abstract)

G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
F. Li , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 456-460
Session 5D - Biochips and DNA-Based nanofabrication

Design automation issues for biofluidic microchips (Abstract)

T. Mukherjee , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 463-470

Design of DNA origami (Abstract)

P.W.K. Rothemund , Comput. Sci. & Comput. & Neural Syst., California Inst. of Technol., Pasadena, CA, USA
pp. 471-478

Kauffman networks: analysis and applications (Abstract)

A. Martinelli , R. Inst. of Technol., Kista, Sweden
M. Teslenko , R. Inst. of Technol., Kista, Sweden
E. Dubrova , R. Inst. of Technol., Kista, Sweden
pp. 479-484
Session 6A - Efficient simulation and synthesis methodologies for analog circuits

Parameterized model order reduction of nonlinear dynamical systems (Abstract)

B. Bond , Res. Lab. in Electron., Massachusetts Inst. of Technol., Cambridge, MA, USA
L. Daniel , R. Inst. of Technol., Kista, Sweden
pp. 487-494

Fast-yet-accurate PVT simulation by combined direct and iterative methods (Abstract)

Bo Hu , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J.R. Shi , R. Inst. of Technol., Kista, Sweden
pp. 495-501

Robust automated synthesis methodology for integrated spiral inductors with variability (Abstract)

A. Nieuwoudt , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Y. Massoud , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 502-507
Session 6B - Technology mapping and timing analysis

Statistical technology mapping for parametric yield (Abstract)

M. Mani , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
A.K. Singh , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Orshansky , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 511-518

Reducing structural bias in technology mapping (Abstract)

S. Chatterjee , Dept. of Electr. Eng. & Comput. Sci.,, UC Berkeley, CA, USA
T. Kam , IBM Syst. & Technol. Group, Austin, TX, USA
X. Wang , Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea
R. Brayton , Dept. of Electr. Eng. & Comput. Sci.,, UC Berkeley, CA, USA
A. Mishchenko , Dept. of Electr. Eng. & Comput. Sci.,, UC Berkeley, CA, USA
pp. 519-526

Improving the efficiency of static timing analysis with false paths (Abstract)

Bo Yao , California Univ., La Jolla, CA, USA
Yi Zhu , California Univ., La Jolla, CA, USA
Hongyu Chen , California Univ., La Jolla, CA, USA
Shuo Zhou , California Univ., La Jolla, CA, USA
Chung-Kuan Cheng , California Univ., La Jolla, CA, USA
pp. 527-531
Session 6C - Power aware system architecture and software optimizations

Total power-optimal pipelining and parallel processing under process variations in nanometer technology (Abstract)

P. Suaris , Intel Corp., Hillsboro, OR, USA
T. Mudge , California Univ., La Jolla, CA, USA
Taeho Kgil , California Univ., La Jolla, CA, USA
K. Bowman , California Univ., La Jolla, CA, USA
V. De , California Univ., La Jolla, CA, USA
pp. 535-540

Serial-link bus: a low-power on-chip bus architecture (Abstract)

Y. Ismail , Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
M. Ghoneima , Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
M. Khellah , California Univ., La Jolla, CA, USA
V. De , California Univ., La Jolla, CA, USA
J. Tschanz , California Univ., La Jolla, CA, USA
pp. 541-546

New decompilation techniques for binary-level co-processor generation (Abstract)

G. Stiff , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 547-554
Session 6D - Cellular array architectures

Eliminating wire crossings for molecular quantum-dot cellular automata implementation (Abstract)

M. Niemier , California Univ., La Jolla, CA, USA
D.Z. Chen , Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
K. Whitton , Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
A. Chaudhary , Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
D.Z. Chen , Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 565-571
Session 7A - Variability aware clocking

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis (Abstract)

Lizheng Zhang , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Lizheng Zhang , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Jeng-Liang Tsai , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 575-581

TACO: temperature aware clock-tree optimization (Abstract)

D.Z. Pan , Dept of ECE, Texas Univ., Austin, TX, USA
S. Ahmedtt , Dept of ECE, Texas Univ., Austin, TX, USA
Minsik Cho , Dept of ECE, Texas Univ., Austin, TX, USA
pp. 582-587

Statistical based link insertion for robust clock network design (Abstract)

W.-C.D. Lam , Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
Y. Chen , California Univ., La Jolla, CA, USA
V. Balakrishnan , Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
J. Jam , Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
C.-K. Koh , Dept. of Electr. & Comput. Eng.,, Purdue Univ., W. Lafayette, IN, USA
pp. 588-591

Practical techniques to reduce skew and its variations in buffered clock networks (Abstract)

Sunil Khatri , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
J. Hu , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
G. Venkataraman , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
N. Jayakumar , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
P. Li , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 592-596
Session 7B - Oscillator analysis

An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators (Abstract)

Ting Mei , Minnesota Univ., Duluth, MN, USA
J. Roychowdhury , Minnesota Univ., Duluth, MN, USA
pp. 599-603

Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators (Abstract)

Ting Mei , Minnesota Univ., Twin Cities, MN, USA
J. Roychowdhury , Minnesota Univ., Twin Cities, MN, USA
pp. 604-609

A multi-harmonic probe technique for computing oscillator steady states (Abstract)

K.D. Boianapally , Dept. of Electr. & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
Ting Mei , Dept. of Electr. & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
J. Roychowdhury , Dept. of Electr. & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
pp. 610-613

Steady-state analysis of voltage and current controlled oscillators (Abstract)

D.C. Lee , Berkeley Design Autom., Santa Clara, CA, USA
Suihua Lu , Berkeley Design Autom., Santa Clara, CA, USA
A. Mehrotra , Berkeley Design Autom., Santa Clara, CA, USA
A. Narayan , Berkeley Design Autom., Santa Clara, CA, USA
pp. 618-623
Session 7C - Power noise and thermal issues

Timing-aware power noise reduction in layout (Abstract)

Chao-Yang Yeh , Apache Design Solutions Inc., Mountain View, CA, USA
M. Marek-Sadowska , Berkeley Design Autom., Santa Clara, CA, USA
pp. 627-634

A high efficiency full-chip thermal simulation algorithm (Abstract)

Yong Zhan , Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
S.S. Sapatnekar , Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
pp. 635-638

Fast thermal simulation for architecture level dynamic thermal management (Abstract)

Wei Wu , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Zhenyu Qi , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Lingling Jin , Berkeley Design Autom., Santa Clara, CA, USA
Hang Li , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Pu Liu , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 639-644

Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality (Abstract)

Peng Li , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 645-651
Session 7D - Nanocomputing

The impact of the nanoscale on computing systems (Abstract)

S.C. Goldstein , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 655-661

Computer-aided design for DNA self-assembly: process and applications (Abstract)

C. Dwyer , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 662-667
Session 8A - Extraction and modeling for interconnect structures

FastSies: a fast stochastic integral equation solver for modeling the rough surface effect (Abstract)

Zhenhai Zhu , Cadence Berkeley Labs, CA, USA
J. White , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 675-682

Efficient statistical capacitance variability modeling with orthogonal principle factor analysis (Abstract)

Wenyin Fu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
J.M. Wang , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Rong Jiang , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C.C.-P. Chen , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
V. Lin , Berkeley Design Autom., Santa Clara, CA, USA
pp. 683-690

Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance (Abstract)

Y. Massoud , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
M. Mondal , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 691-696
Session 8B - Timing and power optimization

Statistical critical path analysis considering correlations (Abstract)

M. Sharma , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
A.J. Strojwas , Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA, USA
Yaping Zhan , Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Newmark , Berkeley Design Autom., Santa Clara, CA, USA
pp. 699-704

Discrete Vt assignment and gate sizing using a self-snapping continuous formulation (Abstract)

D. Blaauw , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
D. Sharma , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
D. Sylvester , Berkeley Design Autom., Santa Clara, CA, USA
A. Srivastava , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
S. Shah , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 705-712

Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs (Abstract)

Sarvesh Bhardwaj , Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Sarma Vrudhula , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 713-718
Session 8C - System-level variability modeling

Projection-based performance modeling for inter/intra-die variations (Abstract)

Xin Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Strojwas , Berkeley Design Autom., Santa Clara, CA, USA
Jiayong Le , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
L.T. Pileggi , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 721-727

System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS) (Abstract)

J.M. Wang , Arizona Univ., Tucson, AZ, USA
Jun Li , Arizona Univ., Tucson, AZ, USA
Dongsheng Ma , Arizona Univ., Tucson, AZ, USA
B. Srinivas , Arizona Univ., Tucson, AZ, USA
C.C.-P. Chen , Arizona Univ., Tucson, AZ, USA
pp. 728-735

Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations (Abstract)

Kunhyuk Kang , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
A. Agarwal , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 736-741
Session 8D - Routing

Thermal via planning for 3-D ICs (Abstract)

Yan Zhang , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
J. Cong , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
pp. 745-752

A routing algorithm for flip-chip design (Abstract)

Yao-Wen Chang , Arizona Univ., Tucson, AZ, USA
Jia-Wei Fang , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
I-Jye Lin , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
Jyh-Herng Wang , Arizona Univ., Tucson, AZ, USA
Ping-Hung Yuh , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 753-758

An escape routing framework for dense boards with high-speed design constraints (Abstract)

M.D.F. Wong , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
M.M. Ozdal , Intel Corp., Hillsboro, OR, USA
P.S. Honsinger , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 759-766

Optimal routing algorithms for pin clusters in high-density multichip modules (Abstract)

M.D.F. Wong , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
M.M. Ozdal , Intel Corp., Hillsboro, OR, USA
P.S. Honsinger , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 767-774
Session 9A - New frontiers in high-level synthesis

Weighted control scheduling (Abstract)

F. Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Aravind Vijayakumar , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 777-783

Hardware synthesis from guarded atomic actions with performance specifications (Abstract)

D.L. Rosenband , CSAIL, Massachusetts Inst. of Technol., USA
D.L. Rosenband , CSAIL, Massachusetts Inst. of Technol., USA
pp. 784-791

Fast timing closure by interconnect criticality driven delay relaxation (Abstract)

L. Singhal , Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
E. Bozorgzadeh , Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 792-797

Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration (Abstract)

V. Balakrishnan , Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Ngai Wong , Dept. of Electr. & Electron. Eng., Hong Kong Univ., China
pp. 801-805

Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations (Abstract)

Peng Li , Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
L.T. Pileggi , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Xin Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 806-812

A more reliable reduction algorithm for behavioral model extraction (Abstract)

D. Vasilyev , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
J. White , Donald Bren Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 813-820

An efficient method for terminal reduction of interconnect circuits considering delay variations (Abstract)

Zhenyu Qi , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
S.X.-D. Tan , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Hang Li , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Jun Kong , Arizona Univ., Tucson, AZ, USA
Pu Liu , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 821-826
Session 9C - Statistical timing analysis

Statistical timing analysis with two-sided constraints (Abstract)

K.R. Heloue , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
F.N. Najm , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 829-836

A unified framework for statistical timing analysis with coupling and multiple input switching (Abstract)

Hai Zhou , Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
D. Sinha , Dept. of Electr. & Comput. Eng.,, Northwestern Univ., Evanston, IL, USA
pp. 837-843

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations (Abstract)

Jiayong Le , Extreme DA, Palo Alto, CA, USA
L.T. Pileggi , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Xin Li , Extreme DA, Palo Alto, CA, USA
Mustafa Celik , Extreme DA, Palo Alto, CA, USA
pp. 844-851
Session 9D - Problem structure in formal verification

Verification of executable pipelined machines with bit-level interfaces (Abstract)

S.K. Srinivasan , Extreme DA, Palo Alto, CA, USA
P. Manolios , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 855-862

A complete compositional reasoning framework for the efficient verification of pipelined machines (Abstract)

S.K. Srinivasan , Extreme DA, Palo Alto, CA, USA
P. Manolios , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 863-870

Post-verification debugging of hierarchical designs (Abstract)

M.F. Ali , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Veneris , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
R. Drechsler , Arizona Univ., Tucson, AZ, USA
M.S. Abadir , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
S. Safarpour , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 871-876

Efficient LTL compilation for SAT-based model checking (Abstract)

S. Egorov , Intel Corp., Moscow, Russia
M.Y. Vardi , Arizona Univ., Tucson, AZ, USA
R. Fraer , Intel Corp., Moscow, Russia
D. Korchemny , Intel Corp., Moscow, Russia
R. Armoni , Intel Corp., Moscow, Russia
pp. 877-884

SAT based solutions for consistency problems in formal property specifications for open systems (Abstract)

Sayantan Das , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Suchismita Roy , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P.P. Chakrabarti , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Pallab Dasgupta , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Prasenjit Basu , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 885-888
Session 10A - Analytical placement

Architecture and details of a high quality, large-scale analytical placer (Abstract)

A.B. Kahng , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Qinke Wang , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
S. Reda , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 891-898

Mixed-size placement via line search (Abstract)

K. Vorwerk , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
A. Kennings , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 899-904

A hybrid linear equation solver and its application in quadratic placement (Abstract)

S.S. Sapatnekar , Minnesota Univ., Minneapolis, MN, USA
Haifeng Qian , Minnesota Univ., Minneapolis, MN, USA
pp. 905-909
Session 10B - Embedded tutorial: hardware and software design of energy efficient sensor platforms

Energy-efficient platform designs for real-world wireless sensing applications (Abstract)

Chulsung Park , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
P.H. Chou , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 913-920

Power-aware microsensor design (Abstract)

M. Bajura , Inf. Sci. Inst., Southern California Univ., Arlington, VA, USA
B. Schott , Inf. Sci. Inst., Southern California Univ., Arlington, VA, USA
pp. 921-924

System software techniques for low-power operation in wireless sensor networks (Abstract)

P.K. Dutta , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
D.E. Culler , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 925-932
Session 10C - Improving the accuracy of static timing analysis

Expanding the frequency range of AWE via time shifting (Abstract)

C. Amin , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
A. Shebaita , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Y. Ismail , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
F. Dartu , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 935-938

A sliding window scheme for accurate clock mesh analysis (Abstract)

C. Yeh , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
H. Nguyen , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
G. Wilke , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
S. Reddy , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
H. Chen , UC San Diego, CA, USA
pp. 939-946

Accurate delay computation for noisy waveform shapes (Abstract)

D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
A. Jain , Michigan Univ., Ann Arbor, MI, USA
V. Zolotov , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 947-953

Pessimism reduction in crosstalk noise aware STA (Abstract)

V. Zolotov , Michigan Univ., Ann Arbor, MI, USA
R. Panda , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
I. Algol , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Grinshpon , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
M. Becer , CLK Design Autom., Littleton, MA, USA
pp. 954-961
Session 10D - Embedded tutorial : formal eguivalence checking between system-level models and RTL

Embedded tutorial: formal equivalence checking between system-level models and RTL (Abstract)

A. Koelbl , Synopsys, Inc., Mountain View, CA, USA
Yuan Lu , Michigan Univ., Ann Arbor, MI, USA
A. Mathur , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 965-971
Session 11A - Embedded tutorial: emergent communication

CDMA/FDMA-interconnects for future ULSI communications (Abstract)

M.F. Chang , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 975-978

The feasibility of on-chip interconnection using antennas (Abstract)

C. Cao , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
K. Kim , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
K.K. O , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Branch , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Mehta , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
B. Floyd , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
S.-H. Hwang , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Bohorquez , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
Y.-R. Ding , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
C.-M. Hung , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
T. Dickson , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
X. Guo , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
M.-H. Hwang , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
H. Wu , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Chen , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
E.-Y. Seok , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
N. Trichy , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
W. Bomstad , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
N. Zhang , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J.-J. Lin , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
D. Bravo , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J. Caserta , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
A. Sugavanam , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
S. Yu , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
R. Li , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
J.E. Brewer , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
L. Gao , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
H. Yoon , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
D.-J. Yang , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
pp. 979-984

Global signaling over lossy transmission lines (Abstract)

J.J. Kang , Michigan Univ., Ann Arbor, MI, USA
M.P. Flynn , Michigan Univ., Ann Arbor, MI, USA
pp. 985-992
Session 11B - Addressing emerging challenges for SoCs

A cache-defect-aware code placement algorithm for improving the performance of processors (Abstract)

F. Fallah , Adv. CAD Technol., Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA
T. Ishihara , Adv. CAD Technol., Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA
pp. 995-1001

Improving scratch-pad memory reliability through compiler-guided data block duplication (Abstract)

G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
F. Li , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
I. Kolcu , Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
pp. 1002-1005

An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems (Abstract)

M. Singh , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
A. Agiwal , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
pp. 1006-1013

Memory access optimization of dynamic binary translation for reconfigurable architectures (Abstract)

M. Singh , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
M. Singh , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
pp. 1014-1020
Session 11C - Statistical optimization

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation (Abstract)

D. Blaauw , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
A. Srivastava , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
S. Shah , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
D. Sylvester , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
K. Chopra , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
pp. 1023-1028

Gate sizing using incremental parameterized statistical timing analysis (Abstract)

N. Venkateswarant , Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
C. Visweswariaht , Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
V. Zolotov , Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
M.R. Guthaus , Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
pp. 1029-1036

Statistical gate sizing for timing yield optimization (Abstract)

N.V. Shenoy , Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
Hai Zhou , Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
D. Sinha , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 1037-1041
Session 11D - Making model checking practical

Simulation-based bug trace minimization with BMC-based refinement (Abstract)

I.L. Markov , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
V. Bertacco , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
Kai-hui Chang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
pp. 1045-1051

Complementary use of runtime validation and model checking (Abstract)

A.A. Bayazit , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 1052-1059

Scalable compositional minimization via static analysis (Abstract)

J. Baumgartner , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Aziz , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, IL, USA
F. Zaraket , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 1060-1067

Transition-by-transition FSM traversal for reachability analysis in bounded model checking (Abstract)

W. Kunz , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
M. Wedler , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
D. Stoffel , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
M.D. Nguyen , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
pp. 1068-1075

Automatic generalized phase abstraction for formal verification (Abstract)

J. Kukula , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
P. Bjesse , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
pp. 1076-1082

Author Index (Abstract)

pp. 1083-1088
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