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Computer-Aided Design, International Conference on (2005)
San Jose, CA, USA
May 31, 2005 to May 31, 2005
ISBN: 0-7803-9254-X
pp: 430-436
R. Vemuri , Dept. of ECECS, Cincinnati Univ., OH, USA
A. Agarwal , Dept. of ECECS, Cincinnati Univ., OH, USA
Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.
R. Vemuri, A. Agarwal, "Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits", Computer-Aided Design, International Conference on, vol. 00, no. , pp. 430-436, 2005, doi:10.1109/ICCAD.2005.1560106
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