The Community for Technology Leaders
Computer-Aided Design, International Conference on (2004)
San Jose, CA, USA
Nov. 7, 2004 to Nov. 11, 2004
ISBN: 0-7803-8702-3
TABLE OF CONTENTS
FrontMatter

ICCAD-2004 Awards (PDF)

pp. null
FrontMatter
FrontMatter

Table of Contents (PDF)

pp. xix-xxxii
Session 1A: Statistical Modeling and Optimization Methodologies

Asymptotic probability extraction for non-normal distributions of circuit performance (Abstract)

Jiayong Le , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P. Gopalakrishnan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Xin Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 2-9

Statistical design and optimization of SRAM cell for yield enhancement (Abstract)

S. Mukhopadhyay , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
H. Mahmoodi , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 10-13

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation (Abstract)

D. Sinha , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 14-19
Session 1B: System-level Energy Management

Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization (Abstract)

P.H. Chou , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
Jinfeng Liu , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 21-28

Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals (Abstract)

P. Feldmann , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 88-92
Session 1B: System-level Energy Management

The effects of energy management on reliability in real-time embedded systems (Abstract)

Dakai Zhu , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
D. Mosse , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
R. Melhem , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 35-40
Session 1C: Eouivalence Verification

Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints (Abstract)

D. Kaiss , Intel, Haifa, Israel
Z. Khasidashvili , Intel, Haifa, Israel
M. Skaba , Intel, Haifa, Israel
Z. Hanna , Intel, Haifa, Israel
pp. 58-65

Checking consistency of C and Verilog using predicate abstraction and induction (Abstract)

D. Kroening , Comput. Syst. Inst., ETH Zurich, Switzerland
E. Clarke , Intel, Haifa, Israel
pp. 66-72
Session 1D: Advances in Interconnect Analysis

SPRIM: structure-preserving reduced-order interconnect macromodeling (Abstract)

R.W. Freund , Dept. of Math., California Univ., Davis, CA, USA
pp. 80-87

Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals (Abstract)

P. Feldmann , IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
F. Liu , Intel, Haifa, Israel
pp. 88-92

Fast simulation of VLSI interconnects (Abstract)

V. Balakrishnan , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Kok Koh , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
J. Jain , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 93-98
Session 2A: Soft Error Rate Analysis

Cost-effective radiation hardening technique for combinational logic (Abstract)

K. Mohanram , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Quming Zhou , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 100-106

Improving soft-error tolerance of FPGA configuration bits (Abstract)

M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
A. Gayasen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
Y. Xie , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
N. Vijaykrishnan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
S. Srinivasan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 107-110
Session 2B: Application Specific Memory and Processor Architecture Design Techniques

Banked scratch-pad memory management for reducing leakage energy consumption (Abstract)

M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
I. Kolcu , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
pp. 120-124

Reducing cache misses by application-specific re-configurable indexing (Abstract)

M. Poncino , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
L. Benini , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
E. Macii , Politecnico di Torino, Italy
K. Patel , Politecnico di Torino, Italy
pp. 125-130

DynamoSim: a trace-based dynamically compiled instruction set simulator (Abstract)

M. Poncino , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 131-136
Session 2C: Embedded Tutorial: The Care and Feeding of Your Statistical Static Timer

The care and feeding of your statistical static timer (PDF)

S.R. Nassif , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
N. Hakim , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
D. Boning , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 138-139
Session 3A: Crosstalk-Aware Timing and Noise Analysis

A robust cell-level crosstalk delay change analysis (Abstract)

Ken Tseng , Cadence Design Syst., San Jose, CA, USA
N. Verghese , Cadence Design Syst., San Jose, CA, USA
I. Keller , Cadence Design Syst., San Jose, CA, USA
pp. 147-154

Timing macro-modeling of IP blocks with crosstalk (Abstract)

Ruiming Chen , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 155-159

Delay noise pessimism reduction by logic correlations (Abstract)

V. Zolotov , Synopsys, Inc., Mountain View, CA, USA
M.R. Becer , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
C. Oh , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
S. Gavrilov , Microstyle, Moscow, Russia
R. Soloviev , Microstyle, Moscow, Russia
A. Glebov , Microstyle, Moscow, Russia
pp. 160-167
Session 3B: System Software Optimizations

Factoring and eliminating common subexpressions in polynomial expressions (Abstract)

A. Hosangadi , California Univ., Santa Barbara, CA, USA
F. Fallah , Microstyle, Moscow, Russia
R. Kastner , Microstyle, Moscow, Russia
pp. 169-174
Session 3B: System Software Optimizations

A quantitative study and estimation models for extensible instructions in embedded processors (Abstract)

J. Henkel , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Parameswarani , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
N. Cheung , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 183-189

Code partitioning for synthesis of embedded applications with phantom (Abstract)

A.C. Nacul , Dept. of Comput. Sci., California Univ., Irvine, CA, USA
T. Givargis , Dept. of Comput. Sci., California Univ., Irvine, CA, USA
pp. 190-196
Session 3C: New Directions in Verification

Formal verification coverage: computing the coverage gap between temporal specifications (Abstract)

A. Banerjee , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
C. Rama Mohan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
A. Das , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P.P. Chakrabarti , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Basu , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Dasgupta , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 198-203

Debugging sequential circuits using Boolean satisfiability (Abstract)

R. Drechsler , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Veneris , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
S. Safarpour , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Smith , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
M. Abadir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
M. Fahim Ali , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 204-209

Towards formal verification of analog designs (Abstract)

S. Gupta , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
B.H. Krogh , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 210-217

Automatic translation of behavioral testbench for fully accelerated simulation (Abstract)

Chong-Min Kyung , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Young-Il Kim , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
pp. 218-221
Session 3D: Algorithms and Modeling Techniques for Bio and Nano Technologies

Architectural-level synthesis of digital microfluidics-based biochips (Abstract)

Fei Su , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 223-228

Simultaneous design and placement of multiplexed chemical processing systems on microchips (Abstract)

T. Mukherjee , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
S. Hauan , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Pfeiffer , Dept. of Chem. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 229-236
Session 4A: Developments in Timing Analysis and Optimization

Computation of signal threshold crossing times directly from higher order moments (Abstract)

C.S. Amin , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Y.I. Ismail , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 246-253

Modeling unbuffered latches for timing analysis (Abstract)

F. Dartu , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Y.I. Ismail , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
C.S. Amin , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
pp. 254-260

A flexibility aware budgeting for hierarchical flow timing closure (Abstract)

M. Ramdani , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
M. Robert , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
O. Omedes , Cadence Design Syst., Inc., San Jose, CA, USA
pp. 261-266
Session 4B: Energy Efficiency and Interconnect Design

A power aware system level interconnect design methodology for latency-insensitive systems (Abstract)

A. Xu , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
H. Schmit , Tabula Inc., Santa Clara, CA, USA
L. Pileggi , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
V. Chandra , Tabula Inc., Santa Clara, CA, USA
pp. 275-282

Exploiting level sensitive latches in wire pipelining (Abstract)

Jiang Hu , Dept. of ECE, Northwestern Univ., Evanston, IL, USA
Min Zhao , Tabula Inc., Santa Clara, CA, USA
V. Seth , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 283-290
Session 4C: Floorplanning for Advanced Technologies

Floorplan design for multi-million gate FPGAs (Abstract)

M.D.F. Wong , Tabula Inc., Santa Clara, CA, USA
Lei Cheng , Dept. of Comput. Sic., Illinois Univ., Urbana, IL, USA
pp. 292-299

Temporal floorplanning using the T-tree formulation (Abstract)

Ping-Hung Yuh , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chia-Lin Yang , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Yao-Wen Chang , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 300-305

A thermal-driven floorplanning algorithm for 3D ICs (Abstract)

Yan Zhang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Jie Wei , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 306-313
Session 4D: Robust Design Tools

A chip-level electrostatic discharge simulation strategy (Abstract)

S.R. Nassif , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J.N. Kozhaya , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S.S. Sapatnekar , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Haifeng Qian , Minnesota Univ., Minneapolis, MN, USA
pp. 315-318

Efficient full-chip thermal modeling and analysis (Abstract)

L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Peng Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Chandra , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
M. Asheghi , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 319-326
Session 5A: Embedded Tutorial: Variability Impact on Design

Process and environmental variation impacts on ASIC timing (Abstract)

J. D. Hayes , IBM Microelectron. Div., USA
P. S. Zuchowski , IBM Microelectron. Div., USA
P. A. Habitz , IBM Microelectron. Div., USA
J. H. Oppold , IBM Microelectron. Div., USA
pp. 336-342

Variability in sub-100nm SRAM designs (Abstract)

R. Heald , Sun Microsystems Inc., Sunnyvale, CA, USA
P. Wang , Sun Microsystems Inc., Sunnyvale, CA, USA
pp. 347-352
Session 5B: Architectural Issues in System Synthesis

Application-specific buffer space allocation for networks-on-chip router design (Abstract)

R. Marculescu , Carnegie Mellon Univ., Pittsburgh, PA, USA
Jingcao Hu , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 354-361

Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems (Abstract)

Z. Peng , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
A. Andrei , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
M. Schmitz , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
P. Eles , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
B.M. Al Hashimi , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 362-369

Hardware/software managed scratchpad memory for embedded system (Abstract)

A. Ignjatovic , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
Andhi Janapsatya , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
Sri Parameswaran , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 370-377
Session 5C: Integrated Placement Applications

Physical placement driven by sequential timing analysis (Abstract)

A.P. Hurst , California Univ., Berkeley, CA, USA
A. Kuehlmann , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
P. Chong , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 379-386

On interactions between routing and detailed placement (Abstract)

D. Jariwala , Dept. of Comput. Sci., Illinois Univ., Chicago, IL, USA
J. Lillis , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 387-393

Routability-driven placement and white space allocation (Abstract)

J. Cong , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
P.H. Madden , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Min Xie , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Kok Koh , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
Chen Li , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 394-401

True crosstalk aware incremental placement with noise map (Abstract)

D.Z. Pan , Dept. of EElectr. & Comput. Eng., Texas Univ., Austin, TX, USA
Haoxing Ren , Dept. of EElectr. & Comput. Eng., Texas Univ., Austin, TX, USA
P.G. Villarubia , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 402-409
Session 5D: Novel Directions in Logic Synthesis

On breakable cyclic definitions (Abstract)

A. Mishchenko , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J.-H.R. Jiang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 411-418

Logical effort based technology mapping (Abstract)

S.S. Sapatnekar , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
S.K. Karandikar , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 419-422

Variability inspired implementation selection problem (Abstract)

A. Srivastava , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Davoodi , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
V. Khandelwal , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 423-427

M-trie: an efficient approach to on-chip logic minimization (Abstract)

R. Mahapatra , Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
S. Ahmand , Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
pp. 428-435
Session 6A: Embedded Tutorial: World-Level Methods in Formal Verification

Verifying properties of hardware and software by predicate abstraction and model checking (PDF)

S.K. Rajamani , Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
R.E. Bryant , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 437-438
Session 6B: Interconnect Coding and Optimization

Soft self-synchronising codes for self-calibrating communication (Abstract)

F. Worm , Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
P. Ienne , Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
P. Thiran , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 440-447
Session 6B: Interconnect Coding and Optimization

Optimal wire retiming without binary search (Abstract)

Hai Zhou , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Chuan Lin , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 452-458
Session 6C: Statistical Timing Methods

Interval-valued reduced order statistical interconnect modeling (Abstract)

R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.D. Ma , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 460-467

Static statistical timing analysis for latch-based pipeline designs (Abstract)

S. Kundu , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Li-C Wang , Dept. of ECE, California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of ECE, California Univ., Santa Barbara, CA, USA
R.A. Rutenbar , Dept. of ECE, California Univ., Santa Barbara, CA, USA
pp. 468-472

Efficient statistical timing analysis through error budgeting (Abstract)

A. Davoodi , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Srivastava , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
V. Khandelwal , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 473-477
Session 6D: New Methods in Power Grid Analysis

Fast flip-chip power grid analysis via locality and grid shells (Abstract)

E. Chiprout , Strategic CAD, Intel Labs., Chandler, AZ, USA
pp. 485-488

HiSIM: hierarchical interconnect-centric circuit simulator (Abstract)

T. Karnik , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Tsung-Hao Chen , Synopsis, Inc., Mountain View, CA, USA
Jeng-Liang Tsai , Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
Jeng-Liang Tsai , Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
pp. 489-496
Session 7A: Advances in SAT-Based Verification

Guiding CNF-SAT search via efficient constraint partitioning (Abstract)

P. Kalla , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
V. Durairaj , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 498-501

Incremental deductive & inductive reasoning for SAT-based bounded model checking (PDF)

M.R. Prasad , Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
M.S. Hsiao , Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece
Liang Zhang , Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
pp. 502-509

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring (Abstract)

M.K. Ganai , NEC Labs. America, Princeton, NJ, USA
A. Gupta , NEC Labs. America, Princeton, NJ, USA
P. Ashar , NEC Labs. America, Princeton, NJ, USA
pp. 510-517
Session 7B: Power and Layout-Driven Logic Optimization

Exact and heuristic approaches to input vector control for leakage power reduction (Abstract)

Feng Gao , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 527-532

Leakage control through fine-grained placement and sizing of sleep transistors (Abstract)

A. Srivastava , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
V. Khandelwal , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 533-536

A vectorless estimation of maximum instantaneous current for sequential circuits (Abstract)

Cheng-Tao Hsieh , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
Shih-Chieh Chang , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
Jian-Cheng Lin , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
pp. 537-540
Session 7C: Advances in Floorplanning and Placement

Unification of partitioning, placement and floorplanning (Abstract)

S. Chaturvedi , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
D.A. Papa , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
I.L. Markov , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S.N. Adya , Synplicity, Inc., Sunnyvale, CA, USA
J.A. Roy , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
pp. 550-557

Multilevel expansion-based VLSI placement with blockages (Abstract)

M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Bo Hu , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 558-564

An analytic placer for mixed-size placement and timing-driven placement (Abstract)

Q. Wang , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
A.B. Kahng , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 565-572

Engineering details of a stable force-directed placer (Abstract)

A. Kennings , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
K. Vorwerk , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
A. Vannelli , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 573-580
Session 7D: Programmable Fabrics for Structured Design

An integrated design flow for a via-configurable gate array (Abstract)

M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Yajun Ran , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 582-589

A metal and via maskset programmable VLSI design methodology using PLAs (Abstract)

N. Jayakumar , Dept. of Ind. Eng., Texas A&M Univ., College Station, TX, USA
S.P. Khatri , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 590-594

Analysis and evaluation of a hybrid interconnect structure for FPGAs (Abstract)

R. Huang , Cincinnati Univ., OH, USA
R. Vemuri , Cincinnati Univ., OH, USA
pp. 595-601

Low-power programmable routing circuitry for FPGAs (Abstract)

J.H. Anderson , Dept. of ECE, Toronto Univ., Ont., Canada
F.N. Najm , Dept. of ECE, Toronto Univ., Ont., Canada
pp. 602-609
Session 8A: New Issues in Clocking

Clock schedule verification under process variations (Abstract)

Hai Zhou , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Ruiming Chen , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 619-625

A novel clock distribution and dynamic de-skewing methodology (Abstract)

A. Kapoor , Dept. of ECE, Colorado Univ., Boulder, CO, USA
N. Jayakumar , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
S.P. Khatri , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 626-631
Session 8B: Innovative Models/Methods in Analog and Digital Diagnosis

On per-test fault diagnosis using the X-fault model (Abstract)

Laung-Terng Wang , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Tokiharu Miyoshi , Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
Seiji Kajihara , Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
K. Kinoshita , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
K.K. Saluja , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Xiaoqing Wen , Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
pp. 633-640

Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search (Abstract)

S. Ozev , Duke Univ., Durham, NC, USA
M. Brooke , Duke Univ., Durham, NC, USA
Fang Liu , Duke Univ., Durham, NC, USA
pp. 641-647

An efficient method for improving the quality of per-test fault diagnosis (Abstract)

Chunsheng Liu , Dept. of Comput. & Electron. Eng., Nebraska-Lincoln Univ., Omaha, NE, USA
pp. 648-651
Session 8C: Estimation and Management of Design Metrics

A unified theory of timing budget management (Abstract)

S. Ghiasi , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S. Choudhuri , Duke Univ., Durham, NC, USA
M. Sarrafzadeh , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
E. Bozorgzadeh , Duke Univ., Durham, NC, USA
pp. 653-659

Dynamic range estimation for nonlinear systems (Abstract)

F.N. Najm , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Bin Wu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 660-667

Power estimation for cycle-accurate functional descriptions of hardware (Abstract)

S. Ravi , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
A. Raghunathan , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
N.K. Jha , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Lin Zhong , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 668-675
Session 8D: Advanced Analog/RF Macromodeling and Simulation

Efficient harmonic balance simulation using multi-level frequency decomposition (Abstract)

L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Peng Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 677-682
Session 8D: Advanced Analog/RF Macromodeling and Simulation

Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking (Abstract)

J. Roychowdhury , Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
Xiaolue Lai , Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
pp. 687-694
Session 9A: Estimation Techniques for Physical Design

FLUTE: fast lookup table based wirelength estimation technique (Abstract)

C. Chu , Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 696-701

Wire-length prediction using statistical techniques (Abstract)

A. Davoodi , Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
A. Srivastava , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
V. Khandelwal , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
J.L. Wong , California Univ., Los Angeles, CA, USA
M. Potkonjak , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 702-705

Accurate estimation of global buffer delay within a floorplan (Abstract)

Jiang Hu , Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA
S.S. Sapatnekar , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
C.N. Sze , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
C.J. Alpert , IBM Corp., Austin, TX, USA
pp. 706-711
Session 9B: Timing Model Validation and Efficient On-Chip Test Compression

Frugal linear network-based test decompression for drastic test cost reductions (Abstract)

Wenjing Rao , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
G. Su , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
pp. 721-725

Design space exploration for aggressive test cost reduction in CircularScan architectures (Abstract)

A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
B. Arslan , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
pp. 726-731
Session 9C: Embedded Tutorial: Emerging Technologies on the Design Manufacturing Interface

Design/process learning from electrical test (Abstract)

B. Koenemann , Cadence Design Syst., Inc., San Jose, CA, USA
pp. 733-738

Backend CAD flows for "restrictive design rules" (Abstract)

G. Northrop , IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Lavin , IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Fook-Luen Heng , IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 739-746
Session 9D: Optimization Techniques for FPGAs and Reconfigurability

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth (Abstract)

M. Teslenko , R. Inst. of Technol., IMIT/KTH, Kista, Sweden
E. Dubrova , R. Inst. of Technol., IMIT/KTH, Kista, Sweden
pp. 748-751

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs (Abstract)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
D. Chen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 752-759

Vdd programmability to reduce FPGA interconnect power (Abstract)

Lei He , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Yan Lin , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Fei Li , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 760-765

Configuration bitstream compression for dynamically reconfigurable FPGAs (Abstract)

Lei He , Sch. of Comput., National Univ. of Singapore, Singapore
Weng-Fai Wong , Sch. of Comput., National Univ. of Singapore, Singapore
T. Mitra , Sch. of Comput., National Univ. of Singapore, Singapore
pp. 766-773
Session 10A: Innovative Methods in High-Level Design

High-level synthesis: an essential ingredient for designing complex ASICs (Abstract)

Weng-Fai Wong , MIT, Cambridge, MA, USA
R.S. Nikhil , Sch. of Comput., National Univ. of Singapore, Singapore
D.L. Rosenband , Sch. of Comput., National Univ. of Singapore, Singapore
N. Dave , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
pp. 775-782

High-level synthesis using computation-unit integrated memories (Abstract)

Chao Huang , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
A. Raghunathan , Sch. of Comput., National Univ. of Singapore, Singapore
S. Ravi , Sch. of Comput., National Univ. of Singapore, Singapore
pp. 783-790

Improved use of the carry-save representation for the synthesis of complex arithmetic circuits (Abstract)

P. Ienne , Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
A.K. Verma , Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
pp. 791-798
Session 10B: Power Analysis and Optimization

A general framework for probabilistic low-power design space exploration considering process variation (Abstract)

D. Sylvester , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
A. Srivastava , Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA
pp. 808-813

Timing analysis considering spatial power/ground level variation (Abstract)

M. Hashimoto , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
J. Yamaguchi , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
H. Onodera , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 814-820
Session 10C: Routing

Simultaneous escape routing and layer assignment for dense PCBs (Abstract)

M.M. Ozdal , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
M.D.F. Wong , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 822-829
Session 10C: Routing

Simultaneous short-path and long-path timing optimization for FPGAs (Abstract)

V. Betz , Toronto Technol. Center, Altera Corp., Toronto, Ont., Canada
R. Fung , Toronto Technol. Center, Altera Corp., Toronto, Ont., Canada
W. Chow , Toronto Technol. Center, Altera Corp., Toronto, Ont., Canada
pp. 838-845
Session 10D: Analog Sizing and Optimization

Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing (Abstract)

K. Antreich , Inst. for Electron. Design Autom., TU Munich, Germany
H. Graeb , Inst. for Electron. Design Autom., TU Munich, Germany
G. Stehr , Inst. for Electron. Design Autom., TU Munich, Germany
pp. 847-854

Robust analog/RF circuit design with projection-based posynomial modeling (Abstract)

P. Gopalakrishnan , Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Pileggi , Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
Yang Xu , Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
Xin Li , Dept. of Electr. & Comput. Eng.,, Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 855-862
Session 11A: Variational Analysis of Interconnects

Variational interconnect analysis via PMTBR (Abstract)

J.R. Phillips , Cadence Berkeley Labs., San Jose, CA, USA
pp. 872-879

Stochastic analysis of interconnect performance in the presence of process variations (Abstract)

P. Ghanta , Dept. of ECE, Arizona Univ., Tucson, AZ, USA
J. Wang , Dept. of ECE, Arizona Univ., Tucson, AZ, USA
S. Vrudhula , Dept. of ECE, Arizona Univ., Tucson, AZ, USA
pp. 880-886

A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance (Abstract)

A. Demir , Dept. of ECE, Arizona Univ., Tucson, AZ, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
Zhenhai Zhu , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 887-891
Session 11B: Test Generation for New Fault Models and Circuits

Minimizing the number of test configurations for FPGAs (Abstract)

E. Chmelar , Center for Reliable Comput., Stanford Univ., Palo Alto, CA, USA
pp. 899-902

SPIN-TEST: automatic test pattern generation for speed-independent circuits (Abstract)

Feng Shi , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Y. Makris , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 903-908
Session 11D: Hierarchical Mixed-Signal Modeling and Design

Analyzing software influences on substrate noise: an ADC perspective (Abstract)

M.J. Irwin , Fujitsu Ltd., Kawasaki, Japan
F. Ghenassia , Samsung, South Korea
N. Vijaykrishnan , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 916-922

Design space exploration for a UMTS front-end exploiting analog platforms (Abstract)

S. Gambini , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
F. Svelto , Fujitsu Ltd., Kawasaki, Japan
F. De Bernarclinis , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Vincis , Fujitsu Ltd., Kawasaki, Japan
pp. 923-930

Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines (Abstract)

G. Wolfe , Cincinnati Univ., OH, USA
R. Vemuri , Cincinnati Univ., OH, USA
pp. 931-938

Author Index (PDF)

pp. 939-942
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