Computer-Aided Design, International Conference on (2004)
San Jose, CA, USA
Nov. 7, 2004 to Nov. 11, 2004
S.N. Adya , Synplicity, Inc., Sunnyvale, CA, USA
S. Chaturvedi , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J.A. Roy , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan
D.A. Papa , Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
I.L. Markov , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature, and improvements by over 10% per paper are still common. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. We propose to integrate min-cut placement with fixed-outline floor-planning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven, fixed-outline floorplanning is invoked. If the latter fails, we undo an earlier partitioning decision, merge adjacent placement regions and re-floorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelength-driven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, we propose that free-shape rectilinear floorplanning can be used with rough module-area estimates before synthesis.
S. Chaturvedi, D. Papa, I. Markov, S. Adya and J. Roy, "Unification of partitioning, placement and floorplanning," Computer-Aided Design, International Conference on(ICCAD), San Jose, CA, USA, 2004, pp. 550-557.