The Community for Technology Leaders
ICCAD-2003. International Conference on Computer Aided Design (2003)
San Jose, CA, USA
Nov. 9, 2003 to Nov. 13, 2003
ISBN: 1-58113-762-1
TABLE OF CONTENTS

ICCAD-2003 Reviewers (PDF)

pp. viii-ix

Adaptive error protection for energy efficiency (Abstract)

Lin Li , Microsyst. Design Lab., Pennsylvania State Univ., USA
N. Vijaykrishnan , Microsyst. Design Lab., Pennsylvania State Univ., USA
M. Kandemir , Microsyst. Design Lab., Pennsylvania State Univ., USA
M.J. Irwin , Microsyst. Design Lab., Pennsylvania State Univ., USA
pp. 2-7

SAMBA-bus: A high performance bus architecture for system-on-chips (Abstract)

Ruibing Lu , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Koh Koh , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 8-12

The Y-architecture for on-chip interconnect: analysis and methodology (Abstract)

Hongyu Chen , CSE Dept., California Univ., La Jolla, CA, USA
Chung-Kuan Cheng , CSE Dept., California Univ., La Jolla, CA, USA
A.B. Kahng , CSE Dept., California Univ., La Jolla, CA, USA
pp. 13-19

Generalized network flow techniques for dynamic voltage scaling in hard real-time systems (Abstract)

V. Swaminathan , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 21-25

Approaching the maximum energy saving on embedded systems with multiple voltages (Abstract)

Shaoxiong Hua , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
Gang Qu , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 26-29

Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems (Abstract)

Le Yan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Jiong Luo , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 30-37

RTL power optimization with gate-level accuracy (Abstract)

Qi Wang , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 39-45

Hardware Scheduling for dynamic adaptability using external profiling and hardware threading (Abstract)

B. Swahn , Tufts Univ., Medford, MA, USA
S. Hassoun , Tufts Univ., Medford, MA, USA
pp. 58-64

Bus-Driven Floorplanning (Abstract)

Hua Xiang , CS Dept., UIUC, Urbana, IL, USA
pp. 66-73

A novel geometric algorithm for fast wire-optimized floorplanning (Abstract)

P.G. Sassone , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S.K. Lim , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 74-80

Placement method targeting predictability robustness and performance (Abstract)

C. Ababei , Electr. & Comput. Eng. Dept., Minnesota Univ., Minneapolis, MN, USA
K. Bazargan , Electr. & Comput. Eng. Dept., Minnesota Univ., Minneapolis, MN, USA
pp. 81-85

Efficient thermal placement of standard cells in 3D ICs using a force directed approach (Abstract)

B. Goplen , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
S. Sapatnekar , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 86-89

Partial core encryption for performance-efficient test of SOCs (Abstract)

O. Sinanoglu , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
pp. 91-94

TAM optimization for mixed-signal SOCs using analog test wrappers (Abstract)

A. Sehgal , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
S. Ozev , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 95-99

Using a distributed rectangle bin-packing approach for core-based SoC test scheduling with power constraints (Abstract)

Yu Xia , Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
M. Chrzanowska-Jeske , Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
Benyi Wang , Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
M. Jeske , Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
pp. 100-105

Moment-based power estimation in very deep submicron technologies (Abstract)

A. Garcia-Ortiz , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
L. Kabulepa , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
T. Murgan , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 107-112

IDAP: a tool for high level power estimation of custom array structures (Abstract)

M. Mamidipaka , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 113-119

Design and CAD challenges in sub-90nm CMOS technologies (Abstract)

K. Bernstein , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Ching-Te Chuang , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Joshi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Puri , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 129-136

Fast cycle-accurate behavioral simulation for pipelined processors using early pipeline evaluation (Abstract)

In-Cheol Park , KAIST, Daejeon, South Korea
Sehyeon Kang , KAIST, Daejeon, South Korea
Yongseok Yi , KAIST, Daejeon, South Korea
pp. 138-141

Generator-based verification (Abstract)

Yunshan Zhu , Adv. Technol. Group Synopsys Inc, Mountain View, CA, USA
pp. 146-153

Efficient generation of monitor circuits for GSTE assertion graphs (Abstract)

A.J. Hu , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 154-159

Weibull based analytical waveform model (Abstract)

C.S. Amin , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 161-168

Equivalent waveform propagation for static timing analysis (Abstract)

M. Hashimoto , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
Y. Yamada , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
H. Onodera , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 169-175

Timing analysis in presence of power supply and ground voltage variations (Abstract)

R. Ahmadi , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
F.N. Najm , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 176-183

Vectorless analysis of supply noise induced delay variation (Abstract)

Sanjay Pant , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 184-191

Array composition and decomposition for optimizing embedded applications (Abstract)

G. Chen , Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Pennsylvania State Univ., University Park, PA, USA
A. Nadgir , Pennsylvania State Univ., University Park, PA, USA
pp. 193-196

Code placement with selective cache activity minimization for embedded real-time software design (Abstract)

Junhyung Um , CAE Center & SoC R&D Center, Samsung Electron., South Korea
pp. 197-200

Energy optimization of distributed embedded processors by combined data compression and functional partitioning (Abstract)

Jinfeng Liu , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
P.H. Chou , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 201-208

Energy-aware fault tolerance in fixed-priority real-time embedded systems (Abstract)

Ying Zhang , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
K. Chakrabarty , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
V. Swaminathan , Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
pp. 209-213

Retiming for wire pipelining in System-On-Chip (Abstract)

Chuan Lin , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Hai Zhou , Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 215-220

Retiming with interconnect and gate delay (Abstract)

C. Chu , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 221-226

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels (Abstract)

Ruibing Lu , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Cheng-Kok Koh , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 227-231

Clock scheduling and clocktree construction for high performance ASICs (Abstract)

S. Held , Res. Inst. for Discrete Math., Bonn Univ., Germany
B. Korte , Res. Inst. for Discrete Math., Bonn Univ., Germany
J. Massberg , Res. Inst. for Discrete Math., Bonn Univ., Germany
M. Ringe , Res. Inst. for Discrete Math., Bonn Univ., Germany
J. Vygen , Res. Inst. for Discrete Math., Bonn Univ., Germany
pp. 232-239

A generalized method for computing oscillator phase noise spectra (Abstract)

P. Vanassche , ESAT, Katholieke Univ., Leuven, Belgium
G. Gielen , ESAT, Katholieke Univ., Leuven, Belgium
W. Sansen , ESAT, Katholieke Univ., Leuven, Belgium
pp. 247-250

Efficient iterative time preconditioners for harmonic balance RF circuit simulation (Abstract)

F. Veerse , Mentor Graphics Ltd, Saint Ismier, France
pp. 251-254

Fredkin/Toffoli templates for reversible logic synthesis (Abstract)

D. Maslov , Fac. of Comput. Sci., New Brunswick Univ., Fredericton, NB, Canada
G.W. Dueck , Fac. of Comput. Sci., New Brunswick Univ., Fredericton, NB, Canada
pp. 256-261

Evaluation of placement techniques for DNA probe array layout (Abstract)

A.B. Kahng , CSE Dept., California Univ., San Diego, La Jolla, CA, USA
pp. 262-269

Physical and reduced-order dynamic analysis of MEMS (Abstract)

S.K. De , Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA
N.R. Aluru , Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA
pp. 270-273

Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs (Abstract)

C.F. Fang , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Tsuhan Chen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 275-282

A scalable application-specific processor synthesis methodology (Abstract)

F. Sun , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 283-290

INSIDE: INstruction Selection/Identification & Design Exploration for extensible processors (Abstract)

Newton Cheung , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
Sri Parameswaran , Sch. of Comput. Sci. & Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 291-297

Fractional cut: improved recursive bisection placement (Abstract)

A. Agnihotri , Dept. of Comput. Sci., SUNY Binghamton, NY, USA
M.C. Yildiz , Dept. of Comput. Sci., SUNY Binghamton, NY, USA
A. Khatkhate , Dept. of Comput. Sci., SUNY Binghamton, NY, USA
A. Mathur , Dept. of Comput. Sci., SUNY Binghamton, NY, USA
S. Ono , Dept. of Comput. Sci., SUNY Binghamton, NY, USA
P.H. Madden , Dept. of Comput. Sci., SUNY Binghamton, NY, USA
pp. 307-310

On whitespace and stability in mixed-size placement and physical synthesis (Abstract)

S.N. Adya , Dept. of Electr. & Eng. Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
I.L. Markov , Dept. of Electr. & Eng. Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 311-318

SATORI-a fast sequential SAT engine for circuits (Abstract)

M.K. Iyer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
G. Parthasarathy , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
K.-T. Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 320-325

CAMA: a multi-valued satisfiability solver (Abstract)

Cong Liu , California Univ., Berkeley, CA, USA
A. Kuehlmann , California Univ., Berkeley, CA, USA
M.W. Moskewicz , California Univ., Berkeley, CA, USA
pp. 326-333

The compositional far side of image computation (Abstract)

Chao Wang , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G.D. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 334-340

Cache optimization for embedded processor cores: an analytical approach (Abstract)

A. Ghosh , Dept. of Comput. Sci., California Univ., Irvine, CA, USA
T. Givargis , Dept. of Comput. Sci., California Univ., Irvine, CA, USA
pp. 342-347

Fault-tolerant techniques for Ambient Intelligent distributed systems (Abstract)

D. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
N.H. Zamora , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P. Stanley-Marbell , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 348-355

Performance efficiency of context-flow system-on-chip platform (Abstract)

R. Beidas , Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Jianwen Zhu , Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 356-361

Amplification of ultrawideband signals (Abstract)

Won Namgoong , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
J. Lerdworatawee , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 363-366

A statistical approach to estimate the dynamic non-linearity parameters of pipeline ADCs (Abstract)

M. Taherzadeh-Sani , Dept. of ECE, Tehran Univ., Iran
R. Lotfi , Dept. of ECE, Tehran Univ., Iran
O. Shoaei , Dept. of ECE, Tehran Univ., Iran
pp. 367-370

Systematic design for power minimization of pipelined analog-to-digital converters (Abstract)

R. Lotfi , Dept of Electr. & Comput. Eng., Tehran Univ., Iran
M. Teherzadeh-Sani , Dept of Electr. & Comput. Eng., Tehran Univ., Iran
M.Y. Azizi , Dept of Electr. & Comput. Eng., Tehran Univ., Iran
O. Shoaei , Dept of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 371-374

A framework for designing reusable analog circuits (Abstract)

D. Liu , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 375-380

A fast crosstalk- and performance-driven multilevel routing system (Abstract)

Tsung-Yi Ho , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 382-387

A min-cost flow based detailed router for FPGAs (Abstract)

Seokjin Lee , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 388-393

Length-matching routing for high-speed printed circuit boards (Abstract)

M.M. Ozdal , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 394-400

Analytical bound for unwanted clock skew due to wire width variation (Abstract)

A. Rajaram , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 401-406

Improving Ariadne's Bundle by following multiple threads in abstraction refinement (Abstract)

Chao Wang , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
Bing Li , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
HoonSang Jin , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G.D. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 408-415

Iterative abstraction using SAT-based BMC with proof analysis (Abstract)

A. Gupta , NEC Lab. America, Princeton, NJ, USA
M. Ganai , NEC Lab. America, Princeton, NJ, USA
Zijiang Yang , NEC Lab. America, Princeton, NJ, USA
P. Ashar , NEC Lab. America, Princeton, NJ, USA
pp. 416-423

Efficient verification of hazard-freedom in gate-level timed asynchronous circuits (Abstract)

C.A. Nelson , Utah Univ., Salt Lake City, UT, USA
C.J. Myers , Utah Univ., Salt Lake City, UT, USA
pp. 424-431

Noise analysis for optical fiber communication systems (Abstract)

A. Demir , Dept. of Electr. & Electron. Eng., Koc Univ., Istanbul, Turkey
pp. 441-445

Analog macromodeling using kernel methods (Abstract)

J. Phillips , Cadence Berkeley Lab., Cadence Design Syst., San Jose, CA, USA
pp. 446-453

A hybrid approach to nonlinear macromodel generation for time-varying analog circuits (Abstract)

Peng Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Xin Li , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Yang Xu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 454-461

Incremental placement for timing optimization (Abstract)

Wonjoon Choi , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
K. Bazargan , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 463-466

A trade-off Oriented placement tool (Abstract)

Huaiyu Xu , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Maogang Wang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Bo-Kyung Choi , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Sarrafzadeh , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 467-471

Optimality and stability study of timing-driven placement algorithms (Abstract)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Romesis , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Min Xie , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 472-478

A probabilistic-based design methodology for nanoscale computation (Abstract)

R.I. Bahar , Div. of Eng., Brown Univ., Providence, RI, USA
J. Mundy , Div. of Eng., Brown Univ., Providence, RI, USA
Jie Chen , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 480-486

Modeling of ballistic carbon nanotube field effect transistors for efficient circuit simulation (Abstract)

A. Raychowdhury , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
S. Mukhopadhyay , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 487-490

Circuit simulation of nanotechnology devices with non-monotonic I-V characteristics (Abstract)

Jiayong Le , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 491-496

A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits (Abstract)

S. Mahapatra , Inst. for Microelectron. & Microsyst., Swiss Fed. Inst. of Technol. Lausanne (EPFL), Switzerland
pp. 497-502

A game theoretic approach to dynamic energy minimization in wireless transceivers (Abstract)

A. Iranli , Dept. of Electr. Eng., Univ. of Southern California, USA
H. Fatemi , Dept. of Electr. Eng., Univ. of Southern California, USA
M. Pedram , Dept. of Electr. Eng., Univ. of Southern California, USA
pp. 504-509

Communication-aware task scheduling and voltage selection for total systems energy minimization (Abstract)

G. Varatkar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 510-517

LRU-SEQ: a novel replacement policy for transition energy reduction in instruction caches (Abstract)

P. Kalla , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
X.S. Hu , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 518-522

Compiler-based register name adjustment for low-power embedded processors (Abstract)

P. Petrov , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 523-527

Gradual relaxation techniques with applications to behavioral synthesis (Abstract)

Zhiru Zhang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Yiping Fan , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Potkonjak , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 529-535

Architectural synthesis Integrated with global placement for multi-cycle communication (Abstract)

Jason Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Yiping Fan , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Guoling Han , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Xun Yang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Zhiru Zhang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 536-543

Binding allocation and floorplanning in low power high-level synthesis (Abstract)

A. Stammermann , OFFIS Res. Inst., Oldenburg, Germany
D. Helms , OFFIS Res. Inst., Oldenburg, Germany
M. Schulte , OFFIS Res. Inst., Oldenburg, Germany
pp. 544-550

A high-level interconnect power model for design space exploration (Abstract)

P. Gupta , Dept. of Electr. Eng., Princeton Univ., NJ, USA
Lin Zhong , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 551-558

A probabilistic approach to buffer insertion (Abstract)

V. Khandelwal , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
A. Davoodi , Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
pp. 560-567

Simultaneous analytic area and power optimization for repeater insertion (Abstract)

G.S. Garcea , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
N.P. van der Meijs , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 568-573

Full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flop insertion (Abstract)

Weiping Liao , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Lei He , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 574-580

Power-optimal simultaneous buffer insertion/sizing and wire sizing (Abstract)

Ruiming Li , Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA
Dian Zhou , Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA
Jin Liu , Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA
pp. 581-586

Dynamic data-bit memory built-in self-repair (Abstract)

M. Nicolaidis , iRoC Techol., Grenoble, France
N. Achouri , iRoC Techol., Grenoble, France
S. Boutobza , iRoC Techol., Grenoble, France
pp. 588-594

FAME: a fault-pattern based memory failure analysis framework (Abstract)

Kuo-Liang Cheng , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Wea Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jih-Nung Lee , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Yung-Fa Chou , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Tsun Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 595-598

Hardware/software co-testing of embedded memories in complex SOCs (Abstract)

Bai Hong Fang , Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
Qiang Xu , Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
N. Nicolici , Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
pp. 599-605

Block-based static timing analysis with uncertainty (Abstract)

A. Devgan , IBM Res., Austin, TX, USA
pp. 607-614

/spl tau/AU: Timing analysis under uncertainty (Abstract)

S. Bhardwaj , Dept. of ECE, Arizona Univ., Tucson, AZ, USA
S.B.K. Vrudhula , Dept. of ECE, Arizona Univ., Tucson, AZ, USA
pp. 615-620

Statistical timing analysis considering spatial correlations using a single PERT-like traversal (Abstract)

Hongliang Chang , Dept. of Comput. Sci. & Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 621-625

Leakage power optimization techniques for ultra deep sub-micron multi-level caches (Abstract)

Nam Sung Kim , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 627-632

Dynamic fault-tolerance and metrics for battery powered, failure-prone systems (Abstract)

P. Stanley-Marbell , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 633-640

Dynamic platform management for configurable platform-based System-on-Chips (Abstract)

Krishna Sekar , Dept. of Electr. & Comput. Eng., California Univ., La Jolla, CA, USA
K. Lahiri , Dept. of Electr. & Comput. Eng., California Univ., La Jolla, CA, USA
S. Dey , Dept. of Electr. & Comput. Eng., California Univ., La Jolla, CA, USA
pp. 641-648

A general s-domain hierarchical network reduction algorithm (Abstract)

S.X.-D. Tan , Dept. of Electr. Eng., California Univ., Riverside, CA, USA
pp. 650-657

Branch merge reduction of RLCM networks (Abstract)

B.N. Sheehan , Mentor Graphics Corp., Wilsonville, OR, USA
pp. 658-664

A Sum-over-Paths impulse-response moment-extraction algorithm for IC-interconnect networks: verification, coupled RC lines (Abstract)

Y.L. Le Coz , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
D. Krishna , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
pp. 665-670

Manufacturing-aware physical design (Abstract)

P. Gupta , Dept. of Electr. & Comput. Eng., California Univ., San Diego, CA, USA
pp. 681-687

A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits (Abstract)

R.M. Rao , Dept. of Electr. Eng. & Comput. Sic., Michigan Univ., Ann Arbor, MI, USA
pp. 689-692

Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level (Abstract)

Y.S. Dhillon , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A.U. Diril , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Hsien-Hsin Sean Lee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 693-700

On the interaction between power-aware FPGA CAD Algorithms (Abstract)

J. Lamoureux , Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada
S.J.E. Wilton , Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada
pp. 701-708

A theory of non-deterministic networks (Abstract)

A. Mishchenko , Dept. of EECS, California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of EECS, California Univ., Berkeley, CA, USA
pp. 709-716

Stable multiway circuit partitioning for ECO (Abstract)

Yangseok Cheon , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 718-725

Multi-objective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization (Abstract)

N. Selvakkumaran , Dept. of Comput. Sci., Minnesota Univ., Duluth, MN, USA
G. Karypis , Dept. of Comput. Sci., Minnesota Univ., Duluth, MN, USA
pp. 726-733

An algorithmic approach for generic parallel adders (Abstract)

Jianhua Liu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
Shuo Zhou , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
Haikun Zhu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
Chung-Kuan Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
pp. 734-740

FROSTY: a fast hierarchy extractor for industrial CMOS circuits (Abstract)

Lei Yang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J.R. Shi , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 741-746

Path delay estimation using power supply transient signals: a comparative study using Fourier and wavelet analysis (Abstract)

A. Singh , Dept. of Comput. Eng., Maryland Univ., Baltimore, MD, USA
J. Tharian , Dept. of Comput. Eng., Maryland Univ., Baltimore, MD, USA
J. Plusquellic , Dept. of Comput. Eng., Maryland Univ., Baltimore, MD, USA
pp. 748-753

Layout-aware scan chain synthesis for improved path delay fault coverage (Abstract)

P. Gupta , Dept. of Electr. & Comput. Eng., California Univ., San Diego, CA, USA
A.B. Kahng , Dept. of Electr. & Comput. Eng., California Univ., San Diego, CA, USA
pp. 754-759

Static verification of test vectors for IR drop failure (Abstract)

A.A. Kokrady , ASIC Product Dev. Center, Texas Instrum. India, Bangalore, India
C.P. Ravikumar , ASIC Product Dev. Center, Texas Instrum. India, Bangalore, India
pp. 760-764

ATPG for noise-induced switch failures in domino logic (Abstract)

R. Kundu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.D. Blanton , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 765-768

Statistical verification of power grids considering process-induced leakage current variations (Abstract)

I.A. Ferzli , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
F.N. Najm , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 770-777

A methodology for the computation of an upper bound on noise current spectrum of CMOS switching activity (Abstract)

A. Nardi , California Univ., Berkeley, CA, USA
Haibo Zeng , California Univ., Berkeley, CA, USA
J.L. Garrett , California Univ., Berkeley, CA, USA
L. Daniel , California Univ., Berkeley, CA, USA
A.L. Sangiovanni-Vincentelli , California Univ., Berkeley, CA, USA
pp. 778-785

SuPREME: substrate and power-delivery reluctance-enhanced macromodel evaluation (Abstract)

Tsung-Hao Chen , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C. Luk , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 786-792

SILCA: fast-yet-accurate time-domain simulation of VLSI circuits with strong parasitic coupling effects (Abstract)

Zhao Li , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J.R. Shi , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 793-799

Multi-domain clock skew scheduling (Abstract)

K. Ravindran , California Univ., Berkeley, CA, USA
A. Kuehlmann , California Univ., Berkeley, CA, USA
pp. 801-808

Clock period minimization of non-zero clock skew circuits (Abstract)

Shih-Hsu Huang , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung-li, Taiwan
Yow-Tyng Nieh , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung-li, Taiwan
pp. 809-812

Minimum-area sequential budgeting for FPGA (Abstract)

Chao-Yang Yeh , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 813-817

ILP models for the synthesis of asynchronous control circuits (Abstract)

J. Carmona , Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 818-825

Analytic modeling of interconnects for deep sub-micron circuits (Abstract)

D. Pamunuwa , Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Kista, Sweden
pp. 835-842

A new surface integral formulation for wideband impedance extraction of 3-D structures (Abstract)

B. Song , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
Zhenhai Zhu , Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 843-847

Switch-factor based loop RLC modeling for efficient timing analysis (Abstract)

Yu Cao , Dept. of electr. Eng. & Comput. Sci., California Univ., UC, Berkeley, CA, USA
pp. 848-853

Adjustable width linear combinational scan vector decompression (Abstract)

C.V. Krishna , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
N.A. Touba , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 863-866

Formal methods for Dynamic Power Management (Abstract)

R.K. Gupta , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 874-881

Large-scale circuit placement: gap and promise (Abstract)

Jason Cong , Dept. of Comput. Sci., UCLA, Los Angeles, CA, USA
pp. 883-890

Multi-million gate FPGA physical design challenges (Abstract)

Maogang Wang , Cadence Design Syst., San Jose, CA, USA
pp. 891-898

Statistical timing analysis for intra-die process variations with spatial correlations (Abstract)

A. Agarwal , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 900-907

A statistical gate-delay model considering intra-gate variability (Abstract)

K. Okada , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
K. Yamaoka , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
H. Onodera , Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 908-913

Statistical clock skew analysis considering intra-die process variations (Abstract)

A. Agarwal , Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Michigan Univ., Ann Arbor, MI, USA
pp. 914-921

Author index (PDF)

pp. 923-927

Keynote (PDF)

pp. x

Foreword (PDF)

pp. iv

Awards (PDF)

pp. v
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