The Community for Technology Leaders
Computer-Aided Design, International Conference on (2003)
San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
ISSN: 1092-3152
ISBN: 1-58113-762-1
TABLE OF CONTENTS

Foreword (PDF)

pp. iv

Awards (PDF)

pp. v

Reviewers (PDF)

pp. viii

Keynote (PDF)

pp. x
Session 1A: Interconnect-Centric SoC Design

Adapative Error Protection for Energy Efficiency (Abstract)

Mahmut Kandemir , Pennsylvania State University, University Park, PA
N. Vijaykrishnan , Pennsylvania State University, University Park, PA
Mary Jane Irwin , Pennsylvania State University, University Park, PA
Lin Li , Pennsylvania State University, University Park, PA
pp. 2

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips (Abstract)

Cheng-Kok Koh , Purdue University, West Lafayette, IN
Ruibing Lu , Purdue University, West Lafayette, IN
pp. 8

The Y-Architecture for On-Chip Interconnect: Analysis and Methodology (Abstract)

Andrew B. Kahng , University of California at San Diego, La Jolla
Chung-Kuan Cheng , University of California at San Diego, La Jolla
Bo Yao , University of California at San Diego, La Jolla
Ion Mandoiu , University of Connecticut, Storrs
Qinke Wang , University of California at San Diego, La Jolla
Hongyu Chen , University of California at San Diego, La Jolla
pp. 13
Session 1B: Energy Optimization using Dynamic Voltage Scaling for Embedded Systems

Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages (Abstract)

Gang Qu , University of Maryland, College Park
Shaoxiong Hua , University of Maryland, College Park
pp. 26

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems (Abstract)

Le Yan , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
Jiong Luo , Princeton University, NJ
pp. 30
Session 1C: New Opportunities in High-Level Synthesis

RTL Power Optimization with Gate-Level Accuracy (Abstract)

Sumit Roy , Calypto Design Systems, Inc, Santa Clara
Qi Wang , Cadence Design Systems, Inc, San Jose
pp. 39

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications (Abstract)

Srivaths Ravi , NEC Laboratories America, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Niraj K. Jha , Princeton University, NJ
Chao Huang , Princeton University, NJ
pp. 46

Achieving Design Closure Through Delay Relaxation Parameter (Abstract)

Majid Sarrafzadeh , University of California, Los Angeles
Seda Ogrenci Memik , University of California, Los Angeles
Ankur Srivastava , University of Maryland, College Park, MD
Bo-Kyung Choi , University of California, Los Angeles
pp. 54

Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading (Abstract)

Soha Hassoun , Tufts University, Medford, MA
Brian Swahn , Tufts University, Medford, MA
pp. 58
Session 1D: New Ideas in Placement and Floorplanning

Bus-Driven Floorplanning (Abstract)

Martin D. F. Wong , UIUC, Urbana, IL
Xiaoping Tang , Cadence Design Systems, San Jose, CA
Hua Xiang , UIUC, Urbana, IL
pp. 66

A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning (Abstract)

Sung K. Lim , Georgia Institute of Technology, Atlanta
Peter G. Sassone , Georgia Institute of Technology, Atlanta
pp. 74

Placement Method Targeting Predictability Robustness and Performance (Abstract)

Kia Bazargan , University of Minnesota, Minneapolis
Cristinel Ababei , University of Minnesota, Minneapolis
pp. 81

Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach (Abstract)

Brent Goplen , University of Minnesota, Minneapolis
Sachin Sapatnekar , University of Minnesota, Minneapolis
pp. 86
Session 2A: Improvements in SoC Testing

Partial Core Encryption for Performance-Efficient Test of SOCs (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 91

TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Sule Ozev , Duke University, Durham, NC
Anuja Sehgal , Duke University, Durham, NC
pp. 95

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints (Abstract)

Yu Xia , Portland State University, OR
Benyi Wang , Portland State University, OR
Malgorzata Chrzanowska-Jeske , Portland State University, OR
Marcin Jeske , Portland State University, OR
pp. 100
Session 2B: Electrical and Power Models - System to Transistor Level

Moment-Based Power Estimation in Very Deep Submicron Technologies (Abstract)

Tudor Murgan , Darmstadt University of Technology
Manfred Glesner , Darmstadt University of Technology
Alberto Garcia-Ortiz , Darmstadt University of Technology
Lukusa Kabulepa , Darmstadt University of Technology
pp. 107

IDAP: A Tool for High Level Power Estimation of Custom Array Structures (Abstract)

Magdy Abadir , Motorola Inc., Austin, TX
Mahesh Mamidipaka , University of California, Irvine
Kamal Khouri , Motorola Inc., Austin, TX
Nikil Dutt , University of California, Irvine
pp. 113

SOI Transistor Model for Fast Transient Simulation (Abstract)

A. Patel , Motorola, Inc. - Austin, TX
D. Nadezhin , MCST - Moscow, Russia
A. Glebov , Microstyle - Moscow, Russia
V. Zolotov , Motorola, Inc. - Austin, TX
M. Becer , Motorola, Inc. - Austin, TX
S. Gavrilov , Microstyle - Moscow, Russia
R. Panda , Motorola, Inc. - Austin, TX
Y. Egorov , Microstyle - Moscow, Russia
D. Blaauw , Univ. of Michigan - Ann Arbor, MI
A. Ardelea , Motorola, Inc. - Austin, TX
pp. 120
Session 2C: Embedded Tutorial: Design and CAD Challenges for sub-90nm CMOS Technology

Design and CAD Challenges in sub-90nm CMOS Technologies (Abstract)

Kerry Bernstein , IBM Thomas J Watson Research Center, Yorktown Hts, NY
Ruchir Puri , IBM Thomas J Watson Research Center, Yorktown Hts, NY
Rajiv Joshi , IBM Thomas J Watson Research Center, Yorktown Hts, NY
Ching-Te Chuang , IBM Thomas J Watson Research Center, Yorktown Hts, NY
pp. 129
Session 3A: Emerging Techniques in Dynamic Verification

Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation (Abstract)

In-Cheol Park , KAIST - Daejeon, Korea
Yongseok Yi , KAIST - Daejeon, Korea
Sehyeon Kang , KAIST - Daejeon, Korea
pp. 138

A Framework for Constrained Functional Verification (Abstract)

Carl Pixley , Synopsys, Hillsboro, OR
Adnan Aziz , University of Texas at Austin
Jun Yuan , Verplex Systems, Milpitas, CA
Ken Albin , Motorola Inc., Austin, TX
pp. 142

Generator-based Verification (Abstract)

James H. Kukula , Synopsys, Inc., Hillsboro, OR
Yunshan Zhu , Synopsys, Inc., Mountain View, CA
pp. 146

Efficient Generation of Monitor Circuits for GSTE Assertion Graphs (Abstract)

Alan J. Hu , University of British Columbia
Jin Yang , Intel Corporation
Jeremy Casas , Intel Corporation
pp. 154
Session 3B: Delay and Signal Modeling for Timing Analysis

Weibull Based Analytical Waveform Model (Abstract)

Yehea I. Ismail , Northwestern Univ., Evanston, IL
Florentin Dartu , Intel Corporation, Hillsboro, OR
Chirayu S. Amin , Northwestern Univ., Evanston, IL
pp. 161

Equivalent Waveform Propagation for Static Timing Analysis (Abstract)

Hidetoshi Onodera , Kyoto University
Masanori Hashimoto , Kyoto University
Yuji Yamada , Kyoto University
pp. 169

Timing Analysis in Presence of Power Supply and Ground Voltage Variations (Abstract)

Rubil Ahmadi , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 176

Vectorless Analysis of Supply Noise Induced Delay Variation (Abstract)

Savithri Sundareswaran , Motorola, Inc., Austin, TX
Vladimir Zolotov , Motorola, Inc., Austin, TX
Rajendran Panda , Motorola, Inc., Austin, TX
Sanjay Pant , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
pp. 184
Session 3C: Software Techniques for Energy and Performance Optimization in Embedded Systems

Array Composition and Decomposition for Optimizing Embedded Applications (Abstract)

M. Kandemir , Pennsylvania State University, University Park, PA
U. Sezer , University of Wisconsin, Madison, WI
G. Chen , Pennsylvania State University, University Park, PA
A. Nadgir , Pennsylvania State University, University Park, PA
pp. 193

Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Vishnu Swaminathan , Duke University, Durham, NC
Ying Zhang , Duke University, Durham, NC
pp. 209
Session 3D: Optimization of Global Interconnects

Retiming for Wire Pipelining in System-On-Chip (Abstract)

Chuan Lin , Northwestern University, Evanston, IL
Hai Zhou , Northwestern University, Evanston, IL
pp. 215

Retiming with Interconnect and Gate Delay (Abstract)

Sampath Dechu , Micron Technology, Inc., Boise, ID
Evangeline F. Y. Young , The Chinese University of Hong Kong
Chris Chu , Iowa State University, Ames
Dennis K. Y. Tong , The Chinese University of Hong Kong
pp. 221

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels (Abstract)

Cheng-Kok Koh , Purdue University, West Lafayette, IN
Ruibing Lu , Purdue University, West Lafayette, IN
pp. 227

Clock Scheduling and Clocktree Construction for High Performance ASICS (Abstract)

Stephan Held , University of Bonn, Germany
Jens Ma?berg , University of Bonn, Germany
Bernhard Korte , University of Bonn, Germany
Jens Vygen , University of Bonn, Germany
Matthias Ringe , IBM Deutschland Entwicklung GmbH
pp. 232
Session 4A: Numerical Methods for Analog Optimization and Analysis

Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification (Abstract)

Michael Pronath , MunEDA GmbH, Germany
Guido Stehr , Technical University of Munich, Germany
Kurt Antreich , Technical University of Munich, Germany
Helmut Graeb , Technical University of Munich, Germany
Frank Schenkel , MunEDA GmbH, Germany
pp. 241

A Generalized Method for Computing Oscillator Phase Noise Spectra (Abstract)

Georges Gielen , Katholieke Universiteit Leuven - ESAT/MICAS, Belgium
Piet Vanassche , Katholieke Universiteit Leuven - ESAT/MICAS, Belgium
Willy Sansen , Katholieke Universiteit Leuven - ESAT/MICAS, Belgium
pp. 247
Session 4B: CAD Algorithms for Emerging Technologies

Fredkin/Toffoli Templates for Reversible Logic Synthesis (Abstract)

D. Michael Miller , University of Victoria, Canada
Gerhard W. Dueck , University of New Brunswick, Fredericton
Dmitri Maslov , University of New Brunswick, Fredericton
pp. 256

Evaluation of Placement Techniques for DNA Probe Array Layout (Abstract)

Sherief Reda , University of California at San Diego
Xu Xu , University of California at San Diego
Andrew B. Kahng , University of California at San Diego
Alex Z. Zelikovsky , Georgia State University
Ion Mandoiu , University of Connecticut
pp. 262

Physical And Reduced-Order Dynamic Analysis of MEMS (Abstract)

S. K. De , University of Illinois at Urbana-Champaign
N. R. Aluru , University of Illinois at Urbana-Champaign
pp. 270
Session 4C: Design Techniques for Customized Processors

Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs (Abstract)

Claire F. Fang , Carnegie Mellon University, Pittsburgh, PA
Tsuhan Chen , Carnegie Mellon University, Pittsburgh, PA
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
pp. 275

A Scalable Application-Specific Processor Synthesis Methodology (Abstract)

Niraj K. Jha , Princeton University, Princeton, NJ
Fei Sun , Princeton University, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Srivaths Ravi , NEC Laboratories America, Princeton, NJ
pp. 283

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors (Abstract)

Newton Cheung , University of New South Wales, Australia
Sri Parameswaran , University of New South Wales, Australia
J? Henkel , NEC Laboratories America, Princeton, NJ
pp. 291
Session 4D: New Improvements in Placement

An Enhanced Multilevel Algorithm for Circuit Placement (Abstract)

Jason Cong , UCLA Computer Science Department
Tony F. Chan , UCLA Mathematics Department
Tim Kong , Magma Design Automation
Joseph R. Shinnerl , UCLA Computer Science Department
Kenton Sze , UCLA Mathematics Department
pp. 299

Fractional Cut: Improved Recursive Bisection Placement (Abstract)

Mehmet Can YILDIZ , SUNY Binghamton Computer Science Department
Ajita Mathur , SUNY Binghamton Computer Science Department
Ateen Khatkhate , SUNY Binghamton Computer Science Department
Patrick H. Madden , SUNY Binghamton Computer Science Department
Ameya Agnihotri , SUNY Binghamton Computer Science Department
Satoshi Ono , SUNY Binghamton Computer Science Department
pp. 307

On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis (Abstract)

Paul G. Villarrubia , IBM, Corporation, Austin, TX
Saurabh N. Adya , University of Michigan, Ann Arbor
Igor L. Markov , University of Michigan, Ann Arbor
pp. 311
Session 5A: Optimizations for Verification Engines

SATORI - A Fast Sequential SAT Engine for Circuits (Abstract)

G. Parthasarathy , University of California - Santa Barbara
M. K. Iyer , University of California - Santa Barbara
K.-T. Cheng , University of California - Santa Barbara
pp. 320

CAMA: A Multi-Valued Satisfiability Solver (Abstract)

Andreas Kuehlmann , University of California at Berkeley; Cadence Berkeley Labs, CA
Matthew W. Moskewicz , University of California at Berkeley
Cong Liu , University of California at Berkeley
pp. 326

The Compositional Far Side of Image Computation (Abstract)

Gary D. Hachtel , University of Colorado at Boulder
Chao Wang , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 334
Session 5B: System Design Concepts

Cache Optimization For Embedded Processor Cores: An Analytical Approach (Abstract)

Tony Givargis , University of California, Irvine
Arijit Ghosh , University of California, Irvine
pp. 342

Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems (Abstract)

Phillip Stanley-Marbell , Carnegie Mellon University, Pittsburgh, PA
Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Nicholas H. Zamora , Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 348

Performance Efficiency of Context-Flow System-on-Chip Platform (Abstract)

Jianwen Zhu , University of Toronto, Canada
Rami Beidas , University of Toronto, Canada
pp. 356
Session 5C: Analog Design and Methodology

Amplification of Ultrawideband Signals (Abstract)

Jongrit Lerdworatawee , University of Southern California
Won Namgoong , University of Southern California
pp. 363

A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs (Abstract)

Mohammad Taherzadeh-Sani , University of Tehran, Iran
Reza Lotfi , University of Tehran, Iran
Omid Shoaei , University of Tehran, Iran
pp. 367

Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters (Abstract)

Omid Shoaei , Univ. of Tehran, Iran
Mohammad Taherzadeh-Sani , Univ. of Tehran, Iran
Reza Lotfi , Univ. of Tehran, Iran
M. Yaser Azizi , Univ. of Tehran, Iran
pp. 371

A Framework for Designing Reusable Analog Circuits (Abstract)

Mark Horowitz , Stanford University, CA
Dean Liu , Stanford University, CA
Stefanos Sidiropoulos , Stanford University, CA; Aeluros Inc., Mt. View, CA
pp. 375
Session 5D: Routing

A Fast Crosstalk- and Performance-Driven Multilevel Routing System (Abstract)

Sao-Jie Chen , National Taiwan University, Taipei
D. T. Lee , Academia Sinica, Taipei, Taiwan
Tsung-Yi Ho , National Taiwan University, Taipei, Taiwan
Yao-Wen Chang , National Taiwan University, Taipei
pp. 382

A Min-Cost Flow Based Detailed Router for FPGAs (Abstract)

Martin D. F. Wong , University of Illinois at Urbana-Champaign
Yongseok Cheon , The University of Texas at Austin
Seokjin Lee , The University of Texas at Austin
pp. 388

Length-Matching Routing for High-Speed Printed Circuit Boards (Abstract)

Muhammet Mustafa Ozdal , Univ. of Illinois at Urbana-Champaign
Martin D. F. Wong , Univ. of Illinois at Urbana-Champaign
pp. 394

Analytical Bound for Unwanted Clock Skew due to Wire Width Variation (Abstract)

Rabi Mahapatra , Texas A&M University
Wei Guo , Institut Fran?ais du P?trole, France
Anand Rajaram , Texas A&M University
Bing Lu , Cadence Design Sys. Inc., New Providence, NJ
Jiang Hu , Texas A&M University
pp. 401
Session 6A: Automatic Abstraction for Formal Verification

Improving Ariadne?s Bundle by Following Multiple Threads in Abstraction Refinement (Abstract)

HoonSang Jin , University of Colorado at Boulder
Chao Wang , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
Bing Li , University of Colorado at Boulder
Gary D. Hachtel , University of Colorado at Boulder
pp. 408

Iterative Abstraction using SAT-based BMC with Proof Analysis (Abstract)

Aarti Gupta , NEC Laboratories America, Princeton, NJ
Malay Ganai , NEC Laboratories America, Princeton, NJ
Zijiang Yang , NEC Laboratories America, Princeton, NJ
Pranav Ashar , NEC Laboratories America, Princeton, NJ
pp. 416

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits (Abstract)

Curtis A. Nelson , University of Utah, Salt Lake City
Chris J. Myers , University of Utah, Salt Lake City
Tomohiro Yoneda , National Institute of Informatics, Tokyo, Japan
pp. 424
Session 6B: Embedded Tutorial: System Level Design and Verification using a Synchronous Lan

System Level Design and Verification Using a Synchronous Language (Abstract)

Michael Kishinevsky , Intel Corp., Hillsboro, OR
G?rard Berry , Esterel Technologies, France
Satnam Singh , Xilinx, San Jose, CA
pp. 433
Session 6C: Nonlinear Modelling of Analog and Optical Systems

Noise Analysis for Optical Fiber Communication Systems (Abstract)

Alper Demir , Ko? University, Istanbul, Turkey
pp. 441

Analog Macromodeling using Kernel Methods (Abstract)

Joel Phillips , Cadence Design Systems, San Jose, CA
Jo? Afonso , Technical University of Lisbon, Portugal
Arlindo Oliveira , Technical University of Lisbon, Portugal
L. Miguel Silveira , Technical University of Lisbon, Portugal
pp. 446

A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits (Abstract)

Xin Li , Carnegie Mellon University, Pittsburgh, PA
Peng Li , Carnegie Mellon University, Pittsburgh, PA
Yang Xu , Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 454
Session 6D: Timing and Tradeoffs in Placement

Incremental Placement for Timing Optimization (Abstract)

Wonjoon Choi , University of Minnesota, Minneapolis
Kia Bazargan , University of Minnesota, Minneapolis
pp. 463

A Trade-off Oriented Placement Tool (Abstract)

Majid Sarrafzadeh , University of California, Los Angeles
Huaiyu Xu , University of California, Los Angeles
Bo-Kyung Choi , University of California, Los Angeles
Maogang Wang , Cadence Design Systems, San Jose, CA
pp. 467

Optimality and Stability Study of Timing-Driven Placement Algorithms (Abstract)

Jason Cong , University of California, Los Angeles
Min Xie , University of California, Los Angeles
Michail Romesis , University of California, Los Angeles
pp. 472
Session 7A: Simulation at the Nanometer Scale

A Probabilistic-Based Design Methodology for Nanoscale Computation (Abstract)

R. Iris Bahar , Brown University, RI
Joseph Mundy , Brown University, RI
Jie Chen , Brown University, RI
pp. 480

Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics (Abstract)

Anirudh Devgan , IBM Research, Austin, TX
Larry Pileggi , CMU, Pittsburgh, PA
Jiayong Le , CMU, Pittsburgh, PA
pp. 491

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits (Abstract)

Kaustav Banerjee , University of California Santa Barbara, CA
Adrian Mihai Ionescu , Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Florent Pegeon , Silvaco Data Systems, France
Santanu Mahapatra , Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
pp. 497
Session 7B: Energy Issues in Systems Design

A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers (Abstract)

Ali Iranli , University of Southern California
Hanif Fatemi , University of Southern California
Massoud Pedram , University of Southern California
pp. 504

Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization (Abstract)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Girish Varatkar , Carnegie Mellon University, Pittsburgh, PA
pp. 510

LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches (Abstract)

Praveen Kalla , Univ. of Notre Dame
Xiaobo Sharon Hu , Univ. of Notre Dame
J? Henkel , NEC Laboratories America Inc.
pp. 518

Compiler-Based Register Name Adjustment for Low-Power Embedded Processors (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 523
Session 7C: Constraint Driven High-Level Synthesis

Gradual Relaxation Techniques with Applications to Behavioral Synthesis (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Yiping Fan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
Zhiru Zhang , University of California, Los Angeles
pp. 529

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication (Abstract)

Guoling Han , University of California, Los Angeles
Zhiru Zhang , University of California, Los Angeles
Yiping Fan , University of California, Los Angeles
Xun Yang , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 536

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis (Abstract)

W. Nebel , Univ. of Oldenburg, Germany
A. Stammermann , OFFIS Research Institute, Germany
M. Schulte , OFFIS Research Institute, Germany
A. Schulz , Univ. of Oldenburg, Germany
D. Helms , OFFIS Research Institute, Germany
pp. 544

A High-level Interconnect Power Model for Design Space Exploration (Abstract)

Niraj K. Jha , Princeton University, NJ
Lin Zhong , Princeton University, NJ
Pallav Gupta , Princeton University, NJ
pp. 551
Session 7D: Optimal Interconnect Synthesis and Analysis

A Probabilistic Approach to Buffer Insertion (Abstract)

Akash Nanavati , University of California at Los Angeles
Vishal Khandelwal , University of Maryland at College Park
Azadeh Davoodi , University of Maryland at College Park
Ankur Srivastava , University of Maryland at College Park
pp. 560

Simultaneous Analytic Area and Power Optimization for Repeater Insertion (Abstract)

Giuseppe S. Garcea , Delft University of Technology, The Netherlands
Ralph H. J. M. Otten , Eindhoven University of Technology, The Netherlands
Nick P. van der Meijs , Delft University of Technology, The Netherlands
pp. 568

Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion (Abstract)

Lei He , University of California, Los Angeles
Weiping Liao , University of California, Los Angeles
pp. 574

Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing (Abstract)

Xuan Zeng , Fudan University, China
Jin Liu , The University of Texas at Dallas
Ruiming Li , The University of Texas at Dallas
Dian Zhou , The University of Texas at Dallas
pp. 581
Session 8A: Memory Testing

Dynamic Data-bit Memory Built-In Self- Repair (Abstract)

S. Boutobza , iRoC Technologies, France
M. Nicolaidis , iRoC Technologies, France
N. Achouri , iRoC Technologies, France
pp. 588

FAME: A Fault-Pattern Based Memory Failure Analysis Framework (Abstract)

Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Jih-Nung Lee , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
Yung-Fa Chou , National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Hsinchu, Taiwan
pp. 595

Hardware/Software Co-testing of Embedded Memories in Complex SOCs (Abstract)

Qiang Xu , McMaster University, Hamilton, Canada
Bai Hong Fang , McMaster University, Hamilton, Canada
Nicola Nicolici , McMaster University, Hamilton, Canada
pp. 599
Session 8B: Statistical Static Timing - I

Block-based Static Timing Analysis with Uncertainty (Abstract)

Anirudh Devgan , IBM Research, Austin, TX
Chandramouli Kashyap , IBM Microelectronics, Austin, TX
pp. 607

τAU: Timing Analysis Under Uncertainty (Abstract)

Sarma B. K. Vrudhula , University of Arizona
David Blaauw , University of Michigan
Sarvesh Bhardwaj , University of Arizona
pp. 615
Session 8C: Power-Aware Design

Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches (Abstract)

David Blaauw , University of Michigan, Ann Arbor
Trevor Mudge , University of Michigan, Ann Arbor
Nam Sung Kim , University of Michigan, Ann Arbor
pp. 627

Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Phillip Stanley-Marbell , Carnegie Mellon University, Pittsburgh, PA
pp. 633

Dynamic Platform Management for Configurable Platform-Based System-on-Chips (Abstract)

Kanishka Lahiri , UC San Diego, La Jolla
Krishna Sekar , UC San Diego, La Jolla
Sujit Dey , UC San Diego, La Jolla
pp. 641
Session 8D: Interconnect Reduction

A General S-Domain Hierarchical Network Reduction Algorithm (Abstract)

Sheldon X.-D. Tan , University of California, Riverside
pp. 650

Branch Merge Reduction of RLCM Networks (Abstract)

Bernard N. Sheehan , Mentor Graphics Corporation, Wilsonville, Oregon
pp. 658

A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines (Abstract)

D. M. Petranovic , LSI Logic Corporation, Milpitas, CA
W. M. Loh , LSI Logic Corporation, Milpitas, CA
Y. L. Le Coz , Rensselaer Polytechnic Institute, Troy, NY
P. Bendix , LSI Logic Corporation, Milpitas, CA
D. Krishna , Rensselaer Polytechnic Institute, Troy, NY
pp. 665
Session 9A: Embedded Tutorial: Mixed Signal DFT: A Concise Overview

Mixed Signal DFT: A Concise Overview (Abstract)

Karim Arabi , PMC-Sierra
Bozena Kaminska , Comet Microsystems
pp. 672
Session 9B: Embedded Tutorial: Manufacturing-Aware Physical Design

Manufacturing-Aware Physical Design (Abstract)

Puneet Gupta , UC San Diego, La Jolla
Andrew B. Kahng , UC San Diego, La Jolla
pp. 681
Session 9C: Cool Topics in Logic Synthesis

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits (Abstract)

Richard B. Brown , University of Michigan, Ann Arbor
Frank Liu , IBM, Austin, TX
Rahul M. Rao , University of Michigan, Ann Arbor
Jeffrey L. Burns , IBM, Austin, TX
pp. 689

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Abdulkadir Utku Diril , Georgia Institute of Technology, Atlanta, GA
Hsien-Hsin Sean Lee , Georgia Institute of Technology, Atlanta, GA
Yuvraj Singh Dhillon , Georgia Institute of Technology, Atlanta, GA
pp. 693

On the Interaction Between Power-Aware FPGA CAD Algorithms (Abstract)

Steven J. E. Wilton , University of British Columbia
Julien Lamoureux , University of British Columbia
pp. 701

A Theory of Non-Deterministic Networks (Abstract)

Alan Mishchenko , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
pp. 709
Session 9D: Graph Algorithmic Approaches to EDA Problems

Stable Multiway Circuit Partitioning for ECO (Abstract)

Seokjin Lee , The University of Texas at Austin
Yongseok Cheon , The University of Texas at Austin
Martin D. F. Wong , University of Illinois at Urbana-Champaign
pp. 718

Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization (Abstract)

Navaratnasothie Selvakkumaran , University of Minnesota, Minneapolis
George Karypis , University of Minnesota, Minneapolis
pp. 726

An Algorithmic Approach for Generic Parallel Adders (Abstract)

Shuo Zhou , University of California, San Diego
Jianhua Liu , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Haikun Zhu , University of California, San Diego
pp. 734

FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits (Abstract)

C.-J. Richard Shi , University of Washington, Seattle
Lei Yang , University of Washington, Seattle
pp. 741
Session 10A: Parametric Considerations in Test Schemes

Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis (Abstract)

Jim Plusquellic , University of Maryland, Baltimore
Abhishek Singh , University of Maryland, Baltimore
Jitin Tharian , University of Maryland, Baltimore
pp. 748

Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage (Abstract)

Andrew B. Kahng , University of California at San Diego
Puneet Sharma , University of California at San Diego
Ion Mandoiu , University of Connecticut, Storrs
Puneet Gupta , University of California at San Diego
pp. 754

Static Verification of Test Vectors for IR Drop Failure (Abstract)

Aman A. Kokrady , Texas Instruments India, Bangalore, India
C. P. Ravikumar , Texas Instruments India, Bangalore, India
pp. 760

ATPG for Noise-Induced Switch Failures in Domino Logic (Abstract)

Rahul Kundu , Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 765
Session 10B: Power-Grid and Substrate Analysis

Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations (Abstract)

Imad A. Ferzli , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 770

A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity (Abstract)

Joshua L. Garrett , University of California, Berkeley
Luca Daniel , University of California, Berkeley
Haibo Zeng , University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley
Alessandra Nardi , University of California, Berkeley
pp. 778

SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation (Abstract)

Charlie Chung-Ping Chen , National Taiwan University
Clement Luk , University of Wisconsin-Madison
Tsung-Hao Chen , University of Wisconsin-Madison
pp. 786

SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects (Abstract)

Zhao Li , University of Washington, Seattle
C.-J. Richard Shi , University of Washington, Seattle
pp. 793
Session 10C: Hot Topics in Logic Synthesis

Multi-Domain Clock Skew Scheduling (Abstract)

Ellen Sentovich , Cadence Berkeley Labs, Berkeley, CA
Kaushik Ravindran , University of California at Berkeley
Andreas Kuehlmann , University of California at Berkeley; Cadence Berkeley Labs, Berkeley, CA
pp. 801

Clock Period Minimization of Non-Zero Clock Skew Circuits (Abstract)

Shih-Hsu Huang , Chung Yuan Christian University, Chung Li, Taiwan
Yow-Tyng Nieh , Chung Yuan Christian University, Chung Li, Taiwan
pp. 809

Minimum-Area Sequential Budgeting for FPGA (Abstract)

Chao-Yang Yeh , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 813

ILP Models for the Synthesis of Asynchronous Control Circuits (Abstract)

Josep Carmona , Universitat Polit?cnica de Catalunya, Spain
Jordi Cortadella , Universitat Polit?cnica de Catalunya, Spain
pp. 818
Session 10D: Interconnect Modeling

Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules (Abstract)

Anne Woo , University of Illinois, Urbana
Andreas C. Cangellaris , University of Illinois, Urbana
Traianos Yioultsis , Aristotle University of Thessaloniki, Greece
pp. 827

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits (Abstract)

Dinesh Pamunuwa , Royal Institute of Technology, Sweden
Shauki Elassaad , Cadence Design Systems, Berkeley, CA
Hannu Tenhunen , Royal Institute of Technology, Sweden
pp. 835

A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures (Abstract)

Ben Song , Massachusetts Institute of Technology, Cambridge
Zhenhai Zhu , Massachusetts Institute of Technology, Cambridge
John D. Rockway , Lawrence Livemore National Laboratory, Berkeley, CA
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 843

Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis (Abstract)

Xiao-dong Yang , Sun Microsystems
Yu Cao , UC Berkeley
Xuejue Huang , Rambus Inc.
Dennis Sylvester , Univ. of Michigan, Ann Arbor
pp. 848
Session 11A: Test Data Reduction Techniques

On Compacting Test Response Data Containing Unknown Values (Abstract)

Janusz Rajski , Mentor Graphic Corporation, Wilsonville, OR
Sudhakar M. Reddy , University of Iowa, Iowa City
Jerzy Tyszer , Poznan University of Technology, Poland
Chen Wang , Mentor Graphic Corporation, Wilsonville, OR
Irith Pomeranz , Purdue University, West Lafayette, IN
pp. 855

Adjustable Width Linear Combinational Scan Vector Decompression (Abstract)

Nur A. Touba , University of Texas, Austin
C. V. Krishna , University of Texas, Austin
pp. 863
Session 11B: Embedded Tutorial: Formal Methods for Dynamic Power Management

Formal Methods for Dynamic Power Management (PDF)

Sandy Irani , UC Irvine
Rajesh K. Gupta , UC San Diego, La Jolla
Sandeep K. Shukla , Virginia Tech, Blacksburg, VA
pp. 874
Session 11C: Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise

Large-Scale Circuit Placement: Gap and Promise (Abstract)

Jason Cong , UCLA Computer Science Department
Tim Kong , Magma Design Automation
Xin Yuan , UCLA Computer Science Department
Min Xie , UCLA Computer Science Department
Joseph R. Shinnerl , UCLA Computer Science Department
pp. 883

Multi-Million Gate FPGA Physical Design Challenges (Abstract)

Salil Raje , Hier Design Inc
Abhishek Ranjan , Hier Design Inc
Maogang Wang , Cadence Design Systems
pp. 891
Session 11D: Statistical Static Timing - II

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations (Abstract)

Aseem Agarwal , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Vladimir Zolotov , Motorola, Inc., Austin, TX
pp. 900

A Statistical Gate-Delay Model Considering Intra-Gate Variability (Abstract)

Kento Yamaoka , Kyoto University
Kenichi Okada , Kyoto University
Hidetoshi Onodera , Kyoto University
pp. 908

Statistical Clock Skew Analysis Considering Intra-Die Process Variations (Abstract)

Aseem Agarwal , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Vladimir Zolotov , Motorola, Inc., Austin, TX
pp. 914

Author Index (PDF)

pp. 922
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