Computer-Aided Design, International Conference on (2003)
San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
Aseem Agarwal , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Vladimir Zolotov , Motorola, Inc., Austin, TX
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for inter- and intra-die process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby a statistical bound on the probability distribution function of the exact circuit delay is computed with linear run time. First, we develop a model for representing inter- and intra-die variations and their spatial correlations. Using this model, we then show how gate delays and arrival times can be represented as a sum of components, such that the correlation information between arrival times and gate delays is preserved. We then show how arrival times are propagated and merged in the circuit to obtain an arrival time distribution that is an upper bound on the distribution of the exact circuit delay. We prove the correctness of the bound and also show how the bound can be improved by propagating multiple arrival times. The proposed algorithms were implemented and tested on a set of benchmark circuits under several process variation scenarios. The results were compared with Monte Carlo simulation and show an accuracy of 3.32% on average over all test cases.
Aseem Agarwal, David Blaauw, Vladimir Zolotov, "Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations", Computer-Aided Design, International Conference on, vol. 00, no. , pp. 900, 2003, doi:10.1109/ICCAD.2003.1257914