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Computer-Aided Design, International Conference on (2003)
San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
ISSN: 1092-3152
ISBN: 1-58113-762-1
pp: 867
Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City
Design-for-testability (DFT ) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.
Irith Pomeranz, Sudhakar M. Reddy, "On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic", Computer-Aided Design, International Conference on, vol. 00, no. , pp. 867, 2003, doi:10.1109/ICCAD.2003.1257910
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