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Computer-Aided Design, International Conference on (2003)
San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
ISSN: 1092-3152
ISBN: 1-58113-762-1
pp: 754
Andrew B. Kahng , University of California at San Diego
Puneet Sharma , University of California at San Diego
Ion Mandoiu , University of Connecticut, Storrs
Puneet Gupta , University of California at San Diego
ABSTRACT
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wirelength overhead. In this paper we consider both dummy flip-flop and wirelength costs, and focus on post-layout formulations that capture the achievable tradeoffs between these costs and delay fault coverage in scan chain synthesis.
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CITATION
Andrew B. Kahng, Puneet Sharma, Ion Mandoiu, Puneet Gupta, "Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage", Computer-Aided Design, International Conference on, vol. 00, no. , pp. 754, 2003, doi:10.1109/ICCAD.2003.1257893
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