San Jose, CA, USA
Nov. 9, 2003 to Nov. 13, 2003
Santanu Mahapatra , Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Kaustav Banerjee , University of California Santa Barbara, CA
Florent Pegeon , Silvaco Data Systems, France
Adrian Mihai Ionescu , Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. Circuit level co-simulations are successfully performed by implementing the SET analytical model in Analog Hardware Description Language (AHDL) of a professional circuit simulator SMARTSPICE. Validation at device and circuit level is carried out by Monte-Carlo simulations. Some novel functionality hybrid CMOS-SET circuit characteristics: (i) SET neuron (ii) Multiple valued logic circuit and (iii) a new Negative Differential Resistance (NDR) circuit, are also predicted by the proposed SET model and analyzed using the new hybrid simulator.
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian Mihai Ionescu, "A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits", ICCAD, 2003, ICCAD-2003. International Conference on Computer Aided Design, ICCAD-2003. International Conference on Computer Aided Design 2003, pp. 497, doi:10.1109/ICCAD.2003.1257857