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Computer-Aided Design, International Conference on (2003)
San Jose, CA
Nov. 9, 2003 to Nov. 13, 2003
ISSN: 1092-3152
ISBN: 1-58113-762-1
pp: 95
Krishnendu Chakrabarty , Duke University, Durham, NC
Sule Ozev , Duke University, Durham, NC
Anuja Sehgal , Duke University, Durham, NC
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle analog cores in a plug-and-play fashion. A test wrapper based on an ADC/DAC pair and a digital configuration circuit is designed for analog cores such that these cores can be accessed through digital TAMs. In this way, there is no dependence on an analog test bus and expensive mixed-signal testers. Experimental results are presented for several ITC'02 SOC test benchmarks to which three analog cores are added. The results show that the testing of analog cores can be interleaved with the testing of digital cores to reduce the overall testing time for a mixed-signal SOC.
Krishnendu Chakrabarty, Sule Ozev, Anuja Sehgal, "TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers", Computer-Aided Design, International Conference on, vol. 00, no. , pp. 95, 2003, doi:10.1109/ICCAD.2003.1257594
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