The Community for Technology Leaders
2002 IEEE/ACM International Conference on Computer Aided Design (ICCAD) (2002)
San Jose, CA, USA
Nov. 10, 2002 to Nov. 14, 2002
ISSN: 1092-3152
ISBN: 0-7803-7607-2
TABLE OF CONTENTS

Comprehensive frequency-dependent substrate noise analysis using boundary element methods (PDF)

Hongmei Li , Illinois Univ., Urbana, IL, USA
J. Carballido , Illinois Univ., Urbana, IL, USA
H.H. Yu , Illinois Univ., Urbana, IL, USA
V.I. Okhmatovski , Illinois Univ., Urbana, IL, USA
E. Rosenbaum , Illinois Univ., Urbana, IL, USA
A.C. Cangellaris , Illinois Univ., Urbana, IL, USA
pp. 2,3,4,5,6,7,8,9

Theoretical and practical validation of combined BEM/FEM substrate resistance modeling (PDF)

E. Schrik , DIMES, Delft Univ. of Technol., Netherlands
P.M. Dewilde , DIMES, Delft Univ. of Technol., Netherlands
N.P. van der Meijs , DIMES, Delft Univ. of Technol., Netherlands
pp. 10,11,12,13,14,15

Minimizing power across multiple technology and design levels (PDF)

T. Sakurai , Center for Collaborative Res. & Inst. of Ind. Sci., Tokyo Univ., Japan
pp. 24,25,26,27

Optimization and control of V/sub DD/ and V/sub TH/ for low-power, high-speed CMOS design (PDF)

T. Kuroda , Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
pp. 28,29,30,31,32,33,34

Methods for true power minimization (PDF)

R.W. Brodersen , California Univ., Berkeley, CA, USA
pp. 35,36,37,38,39,40,41,42

A novel framework for multilevel routing considering routability and performance (PDF)

Shih-Ping Lin , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 44,45,46,47,48,49,50

An enhanced multilevel routing system (PDF)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Xie , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Y. Zhang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 51,52,53,54,55,56,57,58

Track assignment: a desirable intermediate step between global routing and detailed routing (PDF)

S. Batterywala , Synopsys Inc., Mountain View, CA, USA
N. Shenoy , Synopsys Inc., Mountain View, CA, USA
W. Nicholls , Synopsys Inc., Mountain View, CA, USA
H. Zhou , Synopsys Inc., Mountain View, CA, USA
pp. 59,60,61,62,63,64,65,66

ECO algorithms for removing overlaps between power rails and signal wires [IC layout] (PDF)

Hua Xiang , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 67,68,69,70,71,72,73,74

Fast seed computation for reseeding shift register in test pattern compression (PDF)

N. Oh , Synopsys Inc., Mountain View, CA, USA
R. Kapur , Synopsys Inc., Mountain View, CA, USA
T.W. Williams , Synopsys Inc., Mountain View, CA, USA
pp. 76,77,78,79,80,81

On undetectable faults in partial scan circuits (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 82,83,84,85,86

Conflict driven techniques for improving deterministic test pattern generation (PDF)

Chen Wang , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 87,88,89,90,91,92,93

On theoretical and practical considerations of path selection for delay fault testing (PDF)

Jing-Jia Liou , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
L.-C. Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 94,95,96,97,98,99,100

Interface specification for reconfigurable components (PDF)

Satnam Singh , Xilinx Inc, San Jose, CA, USA
pp. 102,103,104,105,106,107,108,109

Interconnect-aware high-level synthesis for low power (PDF)

Lin Zhong , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 110,111,112,113,114,115,116,117

Predictability: definition, analysis and optimization [VLSI design] (PDF)

A. Srivastava , Dept. of Electr. & Comput. Engg, Maryland Univ., College Park, MD, USA
pp. 118,119,120,121

Simplifying Boolean constraint solving for random simulation-vector generation (PDF)

Jun Yuan , Motorola Inc., Austin, TX, USA
K. Albin , Motorola Inc., Austin, TX, USA
A. Aziz , Motorola Inc., Austin, TX, USA
pp. 123,124,125,126,127

Specifying and verifying imprecise sequential datapaths by arithmetic transforms (PDF)

K. Radecka , Concordia Univ., Montreal, Que., Canada
pp. 128,129,130,131

Symbolic pointer analysis (PDF)

Jianwen Zhu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 150,151,152,153,154,155,156,157

Dynamic compilation for energy adaptation (PDF)

P. Unnikrishnan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 158,159,160,161,162,163

Hardware/software partitioning of software binaries (PDF)

G. Stitt , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 164,165,166,167,168,169,170

A novel net weighting algorithm for timing-driven placement (PDF)

T. Kong , Aplus Design Technol. Inc., Los Angeles, CA, USA
pp. 172,173,174,175,176

Timing-driven placement using design hierarchy guided constraint generation (PDF)

Xiaojian Yang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Bo-Kyung Choi , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Sarrafzadeh , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 177,178,179,180

Multi-objective circuit partitioning for cutsize and path-based delay minimization (PDF)

C. Ababei , Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
pp. 181,182,183,184,185

A hybrid ASIC and FPGA architecture (PDF)

P.S. Zuchowski , IBM Microeletronics Div., Essex Junction, VT, USA
C.B. Reynolds , IBM Microeletronics Div., Essex Junction, VT, USA
R.J. Grupp , IBM Microeletronics Div., Essex Junction, VT, USA
pp. 187,188,189,190,191,192,193,194

Managing power and performance for system-on-chip designs using Voltage Islands (PDF)

D.E. Lackey , IBM Microelectron. Div., Essex Junction, VT, USA
P.S. Zuchowski , IBM Microelectron. Div., Essex Junction, VT, USA
T.R. Bednar , IBM Microelectron. Div., Essex Junction, VT, USA
D.W. Stout , IBM Microelectron. Div., Essex Junction, VT, USA
S.W. Gould , IBM Microelectron. Div., Essex Junction, VT, USA
J.M. Cohn , IBM Microelectron. Div., Essex Junction, VT, USA
pp. 195,196,197,198,199,200,201,202

Sub-90 nm technologies-challenges and opportunities for CAD (PDF)

T. Karnik , Circuit Res., Intel Labs., Hillsboro, OR, USA
S. Borkar , Circuit Res., Intel Labs., Hillsboro, OR, USA
V. De , Circuit Res., Intel Labs., Hillsboro, OR, USA
pp. 203,204,205,206

A local circuit topology for inductive parasitics (PDF)

A. Pacelli , Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 208,209,210,211,212,213,214

INDUCTWISE: inductance-wise interconnect simulator and extractor (PDF)

Tsung-Hao Chen , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C. Luk , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Hyungsuk Kim , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
C. Chung-Ping Chen , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 215,216,217,218,219,220

A precorrected-FFT method for simulating on-chip inductance (PDF)

Haitian Hu , Dept. of Electr. & Comput. Eng., Minnesota Univ., Minnieapolis, MN, USA
pp. 221,222,223,224,225,226,227

On the difference between two widely publicized methods for analyzing oscillator phase behavior (PDF)

P. Vanassche , ESAT/MICAS, Katholieke Universiteit Leuven, Belgium
G. Gielen , ESAT/MICAS, Katholieke Universiteit Leuven, Belgium
W. Sansen , ESAT/MICAS, Katholieke Universiteit Leuven, Belgium
pp. 229,230,231,232,233

A behavioral simulation tool for continuous-time /spl Delta//spl Sigma/ modulators (PDF)

K. Francken , Dept. of Electr. Eng., Katholieke Universiteit Leuven, Belgium
M. Vogels , Dept. of Electr. Eng., Katholieke Universiteit Leuven, Belgium
E. Martens , Dept. of Electr. Eng., Katholieke Universiteit Leuven, Belgium
G. Gielen , Dept. of Electr. Eng., Katholieke Universiteit Leuven, Belgium
pp. 234,235,236,237,238,239

Making Fourier-envelope simulation robust (PDF)

J. Roychowdhury , Minnesota Univ., Minneapolis, MN, USA
pp. 240,241,242,243,244,245

Shaping interconnect for uniform current density (PDF)

Muzhou Shao , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 254,255,256,257,258,259

Non-tree routing for reliability and yield improvement (PDF)

A.B. Kahng , Dept. of Comput. Sci. Eng., Univ. of California, La Jolla, CA, USA
Bao Liu , Dept. of Comput. Sci. Eng., Univ. of California, La Jolla, CA, USA
I.I. Mandoiu , Dept. of Comput. Sci. Eng., Univ. of California, La Jolla, CA, USA
pp. 260,261,262,263,264,265,266

Throughput-driven IC communication fabric synthesis (PDF)

Tao Lin , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 274,275,276,277,278,279

Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects (PDF)

H. Shah , Georgia Inst. of Technol., Atlanta, GA, USA
P. Shiu , Georgia Inst. of Technol., Atlanta, GA, USA
B. Bell , Georgia Inst. of Technol., Atlanta, GA, USA
M. Aldredge , Georgia Inst. of Technol., Atlanta, GA, USA
N. Sopory , Georgia Inst. of Technol., Atlanta, GA, USA
J. Davis , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 280,281,282,283,284

Test-model based hierarchical DFT synthesis (PDF)

S. Ramnath , Synopsys Inc., Mountain View, CA, USA
F. Neuveux , Synopsys Inc., Mountain View, CA, USA
M. Hirech , Synopsys Inc., Mountain View, CA, USA
F. Ng , Synopsys Inc., Mountain View, CA, USA
pp. 286,287,288,289,290,291,292,293

Characteristic faults and spectral information for logic BIST (PDF)

Xiaoding Chen , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
M.S. Hsiao , Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
pp. 294,295,296,297,298

A novel scan architecture for power-efficient, rapid test [sequential circuits] (PDF)

O. Sinanoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 299,300,301,302,303

Optimization of a fully integrated low power CMOS GPS receiver (PDF)

P. Vancorenland , Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
P. Coppejans , Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
W. De Cock , Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
P. Leroux , Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
M. Steyaert , Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
pp. 305,306,307,308

Analysis and optimization of substrate noise coupling in single-chip RF transceiver design (PDF)

A. Koukab , Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 309,310,311,312,313,314,315,316

Design of pipeline analog-to-digital converters via geometric programming (PDF)

M. del Mar Hershenson , Barcelona Design, Inc., Spain
pp. 317,318,319,320,321,322,323,324

Transmission line design of clock trees (PDF)

R. Escovar , Mentor Graphics Corp., Beaverton, OR, USA
R. Suaya , Mentor Graphics Corp., Beaverton, OR, USA
pp. 334,335,336,337,338,339,340

On-chip interconnect modeling by wire duplication (PDF)

G. Zhong , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
C.-K. Koh , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 341,342,343,344,345,346

A case for CMOS/nano co-design (PDF)

M.M. Ziegler , Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
M.R. Stan , Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 348,349,350,351,352

Reversible logic circuit synthesis (PDF)

V.V. Shende , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
A.K. Prasad , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
I.L. Markov , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 353,354,355,356,357,358,359,360

Extraction and LVS for mixed-domain integrated MEMS layouts (PDF)

B. Baidya , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Mukherjee , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 361,362,363,364,365,366

Schematic-based lumped parameterized behavioral modeling for suspended MEMS (PDF)

Q. Jing , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Mukherjee , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
G.K. Fedder , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 367,368,369,370,371,372,373

Standby power optimization via transistor sizing and dual threshold voltage assignment (PDF)

M. Ketkar , Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
S.S. Sapatnekar , Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
pp. 375,376,377,378

Power efficiency of voltage scaling in multiple clock multiple voltage cores (PDF)

A. Iyer , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Marculescu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 379,380,381,382,383,384,385,386

Optimized power-delay curve generation for standard cell ICs (PDF)

M. Vujkovic , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
C. Sechen , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
pp. 387,388,389,390,391,392,393,394

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step (PDF)

H. Tennakoon , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
C. Sechen , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
pp. 395,396,397,398,399,400,401,402

A Markov chain sequence generator for power macromodeling (PDF)

Xun Liu , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
M.C. Papaefthymiou , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 404,405,406,407,408,409,410,411

Circuit power estimation using pattern recognition techniques (PDF)

Lipeng Cao , Somerset Design Center, Motorola Inc., Austin, TX, USA
pp. 412,413,414,415,416,417

Estimation of signal arrival times in the presence of delay noise (PDF)

S. Bhardwaj , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 418,419,420,421,422

CAD computation for manufacturability: can we save VLSI technology from itself? (PDF)

M. Lavin , Res. Div., IBM Corp., Yorktown Heights, NY, USA
L. Liebmann , Res. Div., IBM Corp., Yorktown Heights, NY, USA
pp. 424,425,426,427,428,429,430,431

Molecular electronics: devices, systems and tools for gigagate, gigabit chips (PDF)

M. Butts , Cadence Design Syst. Inc., Portland, OR, USA
pp. 433,434,435,436,437,438,439,440

Conflict driven learning in a quantified Boolean satisfiability solver (PDF)

Lintao Zhang , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 442,443,444,445,446,447,448,449

Generic ILP versus specialized 0-1 ILP: an update (PDF)

F.A. Aloul , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
A. Ramani , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
I.L. Markov , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
K.A. Sakallah , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 450,451,452,453,454,455,456,457

Binary time-frame expansion [circuit verification] (PDF)

F. Fallah , Fujitsu Labs. of America, Sunnyvale, CA, USA
pp. 458,459,460,461,462,463,464

Fast methods for simulation of biomolecule electrostatics (PDF)

S.S. Kuo , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 466,467,468,469,470,471,472,473

Efficient mixed-domain analysis of electrostatic MEMS (PDF)

Gang Li , Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA
N.R. Aluru , Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA
pp. 474,475,476,477

Analog circuit sizing based on formal methods using affine arithmetic (PDF)

A. Lemke , Inst. of Microelectron. Syst., Hannover Univ., Germany
L. Hedrich , Inst. of Microelectron. Syst., Hannover Univ., Germany
E. Barke , Inst. of Microelectron. Syst., Hannover Univ., Germany
pp. 486,487,488,489

SiSMA: a statistical simulator for mismatch analysis of MOS ICs (PDF)

G. Biagetti , Dipt. di Elettronica e Autom., Ancona Univ., Italy
S. Orcioni , Dipt. di Elettronica e Autom., Ancona Univ., Italy
L. Signoracci , Dipt. di Elettronica e Autom., Ancona Univ., Italy
C. Turchetti , Dipt. di Elettronica e Autom., Ancona Univ., Italy
P. Crippa , Dipt. di Elettronica e Autom., Ancona Univ., Italy
M. Alessandrini , Dipt. di Elettronica e Autom., Ancona Univ., Italy
pp. 490,491,492,493,494,495,496

Efficient solution space exploration based on segment trees in analog placement with symmetry constraints (PDF)

F. Balasa , Dept. of Comput. Sci., Illinois Univ., Chicago, IL, USA
S.C. Maruvada , Dept. of Comput. Sci., Illinois Univ., Chicago, IL, USA
K. Krishnamoorthy , Dept. of Comput. Sci., Illinois Univ., Chicago, IL, USA
pp. 497,498,499,500,501,502

Post global routing RLC crosstalk budgeting (PDF)

Jinjun Xiong , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Jun Chen , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
J. Ma , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Lei He , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 504,505,506,507,508,509

A technology-independent CAD tool for ESD protection device extraction-ESDExtractor (PDF)

R.Y. Zhan , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
H.G. Feng , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
Q. Wu , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
G. Chen , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
X.K. Guan , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
A.Z. Wang , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
pp. 510,511,512,513

Whirlpool PLAs: a regular logic structure and their synthesis (PDF)

Fan Mo , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 543,544,545,546,547,548,549,550

Metrics for structural logic synthesis (PDF)

P. Kudva , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 551,552,553,554,555,556

Simplification of non-deterministic multi-valued networks (PDF)

A. Mishchenko , Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
pp. 557,558,559,560,561,562

High-level synthesis of distributed logic-memory architectures (PDF)

Chao Huang , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 564,565,566,567,568,569,570,571

An energy-conscious algorithm for memory port allocation (PDF)

P.R. Panda , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
pp. 572,573,574,575,576

Energy efficient address assignment through minimized memory row switching (PDF)

S. Hettiaratchi , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
P.Y.K. Cheung , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
T.J.W. Clarke , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 577,578,579,580,581

Refining switching window by time slots for crosstalk noise calculation (PDF)

Pinhong Chen , Cadence Design Syst. Inc., San Jose, CA, USA
Y. Kukimoto , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 583,584,585,586

Efficient crosstalk noise modeling using aggressor and tree reductions (PDF)

Li Ding , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
D. Blaauw , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 595,596,597,598,599,600

Bit-level scheduling of heterogeneous behavioural specifications (PDF)

M.C. Molina , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
J.M. Mendias , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
R. Hermida , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 602,603,604,605,606,607,608

Coupling-aware high-level interconnect synthesis for low power (PDF)

Chun-Gi Lyuh , Dept. of Electr. Eng. & Comput. Sci., KAIST, South Korea
Taewhan Kim , Dept. of Electr. Eng. & Comput. Sci., KAIST, South Korea
pp. 609,610,611,612,613

Layout-driven resource sharing in high-level synthesis (PDF)

Junhyung Um , Dept. of Electr. Eng. & Comput. Sci., KAIST, South Korea
Jae-hoon Kim , Dept. of Electr. Eng. & Comput. Sci., KAIST, South Korea
Taewhan Kim , Dept. of Electr. Eng. & Comput. Sci., KAIST, South Korea
pp. 614,615,616,617,618

A delay metric for RC circuits based on the Weibull distribution (Abstract)

F. Liu , IBM Austin, TX, USA
C. Kashyap , IBM Austin, TX, USA
C.J. Alpert , IBM Austin, TX, USA
pp. 620,621,622,623,624

WTA - Waveform-based Timing Analysis for deep submicron circuits (PDF)

L. McMurchie , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
C. Sechen , Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
pp. 625,626,627,628,629,630,631

General framework for removal of clock network pessimism (PDF)

J. Zejda , Synopsys Inc., Mountain View, CA, USA
pp. 632,633,634,635,636,637,638,639

Synthesis of custom processors based on extensible platforms (PDF)

Fei Sun , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 641,642,643,644,645,646,647,648

Efficient instruction encoding for automatic instruction set design of configurable ASIPs (PDF)

Jong-eun Lee , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 649,650,651,652,653,654

Synthesis of customized loop caches for core-based embedded systems (PDF)

S. Cotterell , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 655,656,657,658,659,660,661,662

A hierarchical modeling framework for on-chip communication architectures [SOC] (PDF)

Xinping Zhu , Princeton Univ., NJ, USA
S. Malik , Princeton Univ., NJ, USA
pp. 663,664,665,666,667,668,669,670

Topologically constrained logic synthesis (PDF)

S. Sinha , California Univ., Berkeley, CA, USA
pp. 679,680,681,682,683,684,685,686

Resynthesis of multi-level circuits under tight constraints using symbolic optimization (PDF)

V.N. Kravets , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 687,688,689,690,691,692,693

Schedulability analysis of multiprocessor real-time applications with stochastic task execution times (PDF)

S. Manolache , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
P. Eles , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
Z. Peng , Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
pp. 699,700,701,702,703,704,705,706

Leakage power modeling and reduction with data retention (PDF)

Weiping Liao , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 714,715,716,717,718,719

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads (PDF)

S.M. Martin , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 721,722,723,724,725

A realistic variable voltage scheduling model for real-time applications (PDF)

B. Mochocki , Dept. of Comput. Sci. & Eng., Notre Dame Univ., USA
Xiaobo Sharon Hu , Dept. of Comput. Sci. & Eng., Notre Dame Univ., USA
pp. 726,727,728,729,730,731

Frame-based dynamic voltage and frequency scaling for a MPEG decoder (PDF)

Kihwan Choi , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
K. Dantu , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Wei-Chung Cheng , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 732,733,734,735,736,737

Congestion minimization during placement without estimation (PDF)

Bo Hu , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 739,740,741,742,743,744,745

Free space management for cut-based placement [IC layout] (PDF)

C.J. Alpert , IBM Corp., Austin, TX, USA
Gi-Joon Nam , IBM Corp., Austin, TX, USA
P.G. Villarrubia , IBM Corp., Austin, TX, USA
pp. 746,747,748,749,750,751

Incremental placement for layout-driven optimizations on FPGAs (PDF)

D.P. Singh , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
S.D. Brown , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 752,753,754,755,756,757,758,759

Robust and passive model order reduction for circuits containing susceptance elements (PDF)

Hui Zheng , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 761,762,763,764,765,766

Efficient model order reduction via multi-node moment matching (PDF)

Y.I. Ismail , Electr. & Comput. Eng. Dept., Northwestern Univ., Evanston, IL, USA
pp. 767,768,769,770,771,772,773,774

Optimization based passive constrained fitting (PDF)

C.P. Coelho , Dept. of Electr. & Comput. Eng., Tech. Univ. Lisbon, Portugal
pp. 775,776,777,778,779,780

SAT and ATPG: Boolean engines for formal hardware verification (PDF)

A. Biere , Dept. of Comput. Sci., Eidgenossische Tech. Hochschule, Zurich, Switzerland
pp. 782,783,784,785

ATPG-based logic synthesis: an overview (PDF)

Chih-Wei Jim Chang , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 786,787,788,789

The A to Z of SoCs (PDF)

R.A. Bergamaschi , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 791,792,793,794,795,796,797,798

Author index (PDF)

pp. 799,800,801,802
Introduction

Reviewers (PDF)

pp. xxi

Keynote (PDF)

pp. xxiv

Awards (PDF)

pp. xxiii

Foreword (PDF)

pp. iii
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