The Community for Technology Leaders
Computer-Aided Design, International Conference on (2002)
San Jose, California
Nov. 10, 2002 to Nov. 14, 2002
ISSN: 1092-3152
ISBN: 0-7803-7607-2
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. iii

Reviewers (PDF)

pp. xxi

Awards (PDF)

pp. xxiii

Keynote (PDF)

pp. xxiv
Session 1A: Substrate Modeling

Comprehensive frequency-dependent substrate noise analysis using boundary element methods (Abstract)

Andreas C. Cangellaris , University of Illinois at Urbana-Champaign, Urbana, IL
Harry H. Yu , University of Illinois at Urbana-Champaign, Urbana, IL
Jorge Carballido , University of Illinois at Urbana-Champaign, Urbana, IL
Vladimir I. Okhmatovski , University of Illinois at Urbana-Champaign, Urbana, IL
Elyse Rosenbaum , University of Illinois at Urbana-Champaign, Urbana, IL
Hongmei Li , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 2-9

Theoretical and practical validation of combined BEM/FEM substrate resistance modeling (Abstract)

N. P. van der Meijs , Delft University of Technology, DIMES, Circuits and Systems Group Mekelweg 4, Delft, The Netherlands
P. M. Dewilde , Delft University of Technology, DIMES, Circuits and Systems Group Mekelweg 4, Delft, The Netherlands
E. Schrik , Delft University of Technology, DIMES, Circuits and Systems Group Mekelweg 4, Delft, The Netherlands
pp. 10-15

Implicit treatment of substrate and power-ground losses in return-limited inductance extraction (Abstract)

K. L. Shepard , Columbia University New York, NY
Yu Zheng , Columbia University New York, NY
Dipak Sitaram , Cadence Design Systems, New Providence, NJ
pp. 16-22
Session 1B: Invited Session: Design for Low-Power

Methods for true power minimization (Abstract)

Mark A. Horowitz , Stanford University
Vladimir Stojanovic , Stanford University
Borivoje Nikolic , University of California, Berkeley
Dejan Markovic , University of California, Berkeley
Robert W. Brodersen , University of California, Berkeley
pp. 35-42
Session 1C: Routing

A novel framework for multilevel routing considering routability and performance (Abstract)

Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
Shih-Ping Lin , National Chiao Tung University, Hsinchu, Taiwan
pp. 44-50

An enhanced multilevel routing system (Abstract)

Min Xie , UCLA, Los Angeles, CA
Yan Zhang , UCLA, Los Angeles, CA
Jason Cong , UCLA, Los Angeles, CA
pp. 51-58

Track assignment: a desirable intermediate step between global routing and detailed routing (Abstract)

Hai Zhou , Synopsys Inc., Mountain View, CA
Narendra Shenoy , Synopsys Inc., Mountain View, CA
William Nicholls , Synopsys Inc., Mountain View, CA
Shabbir Batterywala , Synopsys Inc., Mountain View, CA
pp. 59-66

ECO algorithms for removing overlaps between power rails and signal wires (Abstract)

Kai-Yuan Chao , Intel Corporation, Hillsboro, Oregon
D. F. Wong , Univ of Illinois at Urbana-Champaign, Urbana, IL
Hua Xiang , Univ of Illinois at Urbana-Champaign, Urbana, IL
pp. 67-74
Session 1D: Advances in Testing

Fast seed computation for reseeding shift register in test pattern compression (Abstract)

Rohit Kapur , Synopsys Inc., Mountain View, CA
T. W. Williams , Synopsys Inc., Mountain View, CA
Nahmsuk Oh , Synopsys Inc., Mountain View, CA
pp. 76-81

On undetectable faults in partial scan circuits (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City, IA
Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 82-86

Conflict driven techniques for improving deterministic test pattern generation (Abstract)

Irith Pomeranz , Purdue University, West Lafayette, IN
Janusz Rajski , Mentor Graphics Corp., Wilsonville, OR
Sudhakar M. Reddy , University of Iowa, Iowa City, IA
Xijiang Lin , Mentor Graphics Corp., Wilsonville, OR
Chen Wang , University of Iowa, Iowa City, IA
pp. 87-93

On theoretical and practical considerations of path selection for delay fault testing (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
Jing-Jia Liou , University of California, Santa Barbara
pp. 94-100
Session 2A: Novel Ideas in High Level Synthesis

Interface specification for reconfigurable components (Abstract)

Satnam Singh , Xilinx Inc, San Jose, California
pp. 102-109

Interconnect-aware high-level synthesis for low power (Abstract)

Niraj K. Jha , Princeton University, Princeton, NJ
Lin Zhong , Princeton University, Princeton, NJ
pp. 110-117

Predictability: definition, ananlysis and optimization (Abstract)

Majid Sarrafzadeh , University of California at Los Angeles
Ankur Srivastava , University of Maryland, College Park
pp. 118-121
Session 2B: Formal Techniques for Validation and Synthesis

Simplifying Boolean constraint solving for random simulation-vector generation (Abstract)

Adnan Aziz , University of Texas at Austin, Austin, TX
Ken Albin , Motorola Inc., Austin, TX
Carl Pixley , Synopsys, Hillsboro, OR
Jun Yuan , Motorola Inc., Austin, TX
pp. 123-127

Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms (Abstract)

Zeljko Zilic , McGill University, Montreal, Quebec, Canada
Katarzyna Radecka , Concordia University, Montreal, Quebec, Canada
pp. 128-131

Convertibility verification and converter synthesis: two faces of the same coin (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley, Berkeley, CA
Thomas A. Henzinger , University of California, Berkeley, Berkeley, CA
Luca de Alfaro , University of California, Santa Cruz, Santa Cruz, CA
Roberto Passerone , Cadence Berkeley Laboratories, Berkeley, CA
pp. 132-139
Session 2C: Embedded Tutorial: Subthreshold Leakage Modeling and Reduction Techniques

Subthreshold leakage modeling and reduction techniques (Abstract)

Anantha Chandrakasan , Massachusetts Institute of Technology
Siva Narendra , Intel Labs
James Kao , Silicon Labs
pp. 141-148
Session 3A: Compilation Techniques for Hardware/Software Codesign

Symbolic pointer analysis (Abstract)

Jianwen Zhu , University of Toronto, Ontario, Canada
pp. 150-157

Dynamic compilation for energy adaptation (Abstract)

M. Kandemir , The Pennsylvania State University, University Park, PA
D. R. Mudgett , The Pennsylvania State University, University Park, PA
G. Chen , The Pennsylvania State University, University Park, PA
P. Unnikrishnan , The Pennsylvania State University, University Park, PA
pp. 158-163

Hardware/software partitioning of software binaries (Abstract)

Frank Vahid , University of California, Riverside
Greg Stitt , University of California, Riverside
pp. 164-170
Session 3B: Timing-Driven Placement

A novel net weighting algorithm for timing-driven placement (Abstract)

Tim (Tianming) Kong , Aplus Design Technologies, Inc., Los Angeles, CA
pp. 172-176

Timing-driven placement using design hierarchy guided constraint generation (Abstract)

Majid Sarrafzadeh , University of California, Los Angeles, CA
Bo-Kyung Choi , University of California, Los Angeles, CA
Xiaojian Yang , University of California, Los Angeles, CA
pp. 177-180

Multi-objective circuit partitioning for cutsize and path-based delay minimization (Abstract)

Kia Bazargan , University of Minnesota, Minneapolis, MN
Navaratnasothie Selvakkumaran , University of Minnesota, Minneapolis, MN
George Karypis , University of Minnesota, Minneapolis, MN
Cristinel Ababei , University of Minnesota, Minneapolis, MN
pp. 181-185
Session 3C: Invited Session: Emerging Technology Opportunities and Challenges

A hybrid ASIC and FPGA architecture (Abstract)

Bill Troxel , Xilinx Corporation, Boulder, Colorado
Brendan Cremen , Xilinx Corporation, Dublin, Ireland
Christopher B. Reynolds , IBM Microelectronics Division, Essex Junction, Vermont
Richard J. Grupp , IBM Microelectronics Division, Essex Junction, Vermont
Shelly G. Davis , Xilinx Corporation, San Jose, California,
Paul S. Zuchowski , IBM Microelectronics Division, Essex Junction, Vermont
pp. 187-194

Managing power and performance for System-on-Chip designs using Voltage Islands (Abstract)

John M. Cohn , IBM Microelectronics Division, Essex Junction, Vermont
Douglas W. Stout , IBM Microelectronics Division, Essex Junction, Vermont
Paul S. Zuchowski , IBM Microelectronics Division, Essex Junction, Vermont
Scott W. Gould , IBM Microelectronics Division, Essex Junction, Vermont
Thomas R. Bednar , IBM Microelectronics Division, Essex Junction, Vermont
David E. Lackey , IBM Microelectronics Division, Essex Junction, Vermont
pp. 195-202

Sub-90nm technologies: challenges and opportunities for CAD (Abstract)

Shekhar Borkar , Intel Labs, Hillsboro, OR
Vivek De , Intel Labs, Hillsboro, OR
Tanay Karnik , Intel Labs, Hillsboro, OR
pp. 203-206
Session 3D: Inductance Modeling I

A local circuit topology for inductive parasitics (Abstract)

Andrea Pacelli , State University of New York at Stony Brook, Stony Brook, NY
pp. 208-214

INDUCTWISE: inductance-wise interconnect simulator and extractor (Abstract)

Clement Luk , University of Wisconsin-Madison
Charlie Chung-Ping Chen , University of Wisconsin-Madison
Hyungsuk Kim , University of Wisconsin-Madison
Tsung-Hao Chen , University of Wisconsin-Madison
pp. 215-220

A precorrected-FFT method for simulating on-chip inductance (Abstract)

Kaushik Gala , Motorola, Inc., Austin, TX
Min Zhao , Motorola, Inc., Austin, TX
Rajendran Panda , Motorola, Inc., Austin, TX
Sachin S. Sapatnekar , University of Minnesota, Minneapolis, MN
Vladimir Zolotov , Motorola, Inc., Austin, TX
David T. Blaauw , University of Michigan, Ann Arbor, MI
Haitian Hu , University of Minnesota, Minneapolis, MN
pp. 221-227
Session 4A: Efficient Simulation for Analog and RF

On the difference between two widely publicized methods for analyzing oscillator phase behavior (Abstract)

Willy Sansen , Katholieke Universiteit Leuven - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
Piet Vanassche , Katholieke Universiteit Leuven - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
pp. 229-233

A Behavioral Simulation Tool for Continuous-Time \Delta\Sigma Modulators (Abstract)

K. Francken , Katholieke Universiteit Leuven, Belgium
M. Vogels , Katholieke Universiteit Leuven, Belgium
E. Martens , Katholieke Universiteit Leuven, Belgium
G. Gielen , Katholieke Universiteit Leuven, Belgium
pp. 234-239

Making Fourier-Envelope Simulation Robust (Abstract)

Jaijeet Roychowdhury , University of Minnesota
pp. 240-245
Session 4B: Interconnect Optimization

Optimal buffered routing path constructions for single and multiple clock domain systems (Abstract)

Charles J. Alpert , IBM Austin Research Laboratory, Austin, TX
Meera Thiagarajan , Tufts University, Medford, MA
Soha Hassoun , Tufts University, Medford, MA
pp. 247-253

Shaping interconnect for uniform current density (Abstract)

Li-Pen Yuan , Synopsys, Inc., Mountain View, CA
Youxin Gao , Synopsys, Inc., Mountain View, CA
Huijing Cao , Motorola, Inc., Xiqing EDA, Tianjin, China
D. F. Wong , University of Illinois at Urbana-Champaign, Urbana, IL
Muzhou Shao , University of Texas at Austin, Austin, TX
pp. 254-259

Non-tree routing for reliability and yield improvement (Abstract)

Bao Liu , UCSD, La Jolla, CA
Ion I. Maandoiu , UCSD, La Jolla, CA
Andrew B. Kahng , UCSD, La Jolla, CA
pp. 260-266
Session 4C: Chip-Level Communication Structures

Throughput-driven IC communication fabric synthesis (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Tao Lin , Carnegie Mellon University, Pittsburgh, PA
pp. 274-279

Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects (Abstract)

Brian Bell , Georgia Institute of Technology, Atlanta, GA
Mamie Aldredge , Georgia Institute of Technology, Atlanta, GA
Namarata Sopory , Georgia Institute of Technology, Atlanta, GA
Pun Shiu , Georgia Institute of Technology, Atlanta, GA
Harshit Shah , Georgia Institute of Technology, Atlanta, GA
pp. 280-284
Session 4D: New DFT Techniques and Methodogies

Test-model based hierarchical DFT synthesis (Abstract)

Mokhtar Hirech , Synopsys Inc., Mountain View, CA
Felix Ng , Synopsys Inc., Mountain View, CA
Frederic Neuveux , Synopsys Inc., Mountain View, CA
Sanjay Ramnath , Synopsys Inc., Mountain View, CA
pp. 286-293

Characteristic faults and spectral information for logic BIST (PDF)

Michael S. Hsiao , Virginia Tech, Blacksburg, VA
Xiaoding Chen , Virginia Tech, Blacksburg, VA
pp. 294-298

A novel scan architecture for power-efficient, rapid test (Abstract)

Alex Orailoglu , University of California, San Diego, La Jolla, CA
Ozgur Sinanoglu , University of California, San Diego, La Jolla, CA
pp. 299-303
Session 5A: System-Level Analog Design

Optimization of a fully integrated low power CMOS GPS receiver (Abstract)

Michiel Steyaert , Katholieke Universiteit Leuven, ESAT MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Paul Leroux , Katholieke Universiteit Leuven, ESAT MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Philippe Coppejans , Katholieke Universiteit Leuven, ESAT MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Wouter De Cock , Katholieke Universiteit Leuven, ESAT MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Peter Vancorenland , Katholieke Universiteit Leuven, ESAT MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
pp. 305-308

Analysis and optimization of substrate noise coupling in single-chip RF transceiver design (Abstract)

Kaustav Banerjee , University of California, Santa Barbara, CA
Michel Declercq , Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland,
Adil Koukab , Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
pp. 309-316
Session 5B: Inductance Modelling II

Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect (Abstract)

Jacob White , Massachusetts Instit. of Tech.
Alberto Sangiovanni-Vincentelli , Univ. of California, Berkeley
Luca Daniel , Massachusetts Instit. of Tech.
pp. 326-333

Transmission line design of clock trees (Abstract)

Robert Suaya , Mentor Graphics
Rafael Escovar , Mentor Graphics
pp. 334-340

On-chip interconnect modeling by wire duplication (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
Guoan Zhong , Purdue University, West Lafayette, IN
pp. 341-346
Session 5C: Emerging Technologies: Circuits and Systems

A Case for CMOS/nano co-design (Abstract)

Mircea R. Stan , University of Virginia, Charlottesville, VA
Matthew M. Ziegler , University of Virginia, Charlottesville, VA
pp. 348-352

Reversible logic circuit synthesis (Abstract)

Igor L. Markov , University of Michigan, Ann Arbor, MI
John P. Hayes , University of Michigan, Ann Arbor, MI
Aditya K. Prasad , University of Michigan, Ann Arbor, MI
Vivek V. Shende , University of Michigan, Ann Arbor, MI
pp. 353-360

Extraction and LVS for mixed-domain integrated MEMS layouts (Abstract)

Tamal Mukherjee , Carnegie Mellon University, Pittsburgh, PA
Bikram Baidya , Carnegie Mellon University, Pittsburgh, PA
pp. 361-366

Schematic-based lumped parameterized behavioral modeling for suspended MEMS (Abstract)

Tamal Mukherjee , Carnegie Mellon University, Pittsburgh, PA
Gary K. Fedder , Carnegie Mellon University, Pittsburgh, PA
Qi Jing , Carnegie Mellon University, Pittsburgh, PA
pp. 367-373
Session 5D: Low Power and Transistor Level Optimization

Standby power optimization via transistor sizing and dual threshold voltage assignment (Abstract)

Sachin S. Sapatnekar , University of Minnesota Minneapolis, MN
Mahesh Ketkar , University of Minnesota Minneapolis, MN
pp. 375-378

Power efficiency of voltage scaling in multiple clock, multiple voltage cores (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Anoop Iyer , Carnegie Mellon University, Pittsburgh, PA
pp. 379-386

Optimized power-delay curve generation for standard cell ICs (Abstract)

Carl Sechen , University of Washington, Seattle, WA
Miodrag Vujkovic , University of Washington, Seattle, WA
pp. 387-394

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step (Abstract)

Carl Sechen , University of Washington, Seattle, WA
Hiran Tennakoon , University of Washington, Seattle, WA
pp. 395-402
Session 6A: Statistical Techniques for Power and Timing Estimation

A Markov chain sequence generator for power macromodeling (Abstract)

Marios C. Papaefthymiou , University of Michigan, Ann Arbor, Michigan
Xun Liu , University of Michigan, Ann Arbor, Michigan
pp. 404-411

Circuit power estimation using pattern recognition techniques (Abstract)

Lipeng Cao , Somerset Design Center, Motorola Inc Austin, TX
pp. 412-417

Estimation of signal arrival times in the presence of delay noise (Abstract)

Sarma B. K. Vrudhula , University of Arizona
David Blaauw , University of Michigan
Sarvesh Bhardwaj , University of Arizona
pp. 418-422
Session 6B: Embedded Tutorial: CAD Computation for Manufacturability: Can We Save VLSI Technology From Itself?

CAD computation for manufacturability: can we save VLSI technology from itself? (Abstract)

Lars Liebmann , IBM Corporation, Yorktown Heights NY
Mark Lavin , IBM Corporation, Yorktown Heights NY
pp. 424-431
Session 6C: Embedded Tutorial: Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips

Molecular electronics: devices, systems and tools for gigagate, gigabit chips (Abstract)

Seth Copen Goldstein , Carnegie Mellon University, Pittsburgh, PA
Andr? DeHon , California Institute of Technology, Pasadena, CA
Michael Butts , Cadence Design Systems, Inc., Portland, OR
pp. 433-440
Session 7A: Satisfiability Checking

Conflict driven learning in a quantified Boolean Satisfiability solver (Abstract)

Sharad Malik , Princeton University
Lintao Zhang , Princeton University
pp. 442-449

Generic ILP versus specialized 0-1 ILP: an update (Abstract)

Igor L. Markov , University of Michigan, Ann Arbor, MI
Karem A. Sakallah , University of Michigan, Ann Arbor, MI
Arathi Ramani , University of Michigan, Ann Arbor, MI
Fadi A. Aloul , University of Michigan, Ann Arbor, MI
pp. 450-457

Binary Time-Frame Expansion (Abstract)

Farzan Fallah , Fujitsu Labs. of America, Sunnyvale, CA
pp. 458-464
Session 7B: Emerging Technologies: Device Modeling and Simulation

Fast methods for simulation of biomolecule electrostatics (Abstract)

Jacob K. White , Massachusetts Institute of Technology, Cambridge, MA
Bruce Tidor , Massachusetts Institute of Technology, Cambridge, MA
Jaydeep P. Bardhan , Massachusetts Institute of Technology, Cambridge, MA
Michael D. Altman , Massachusetts Institute of Technology, Cambridge, MA
Shihhsien S. Kuo , Massachusetts Institute of Technology, Cambridge, MA
pp. 466-473

Efficient mixed-domain analysis of electrostatic MEMS (Abstract)

N. R. Aluru , University of Illinois at Urbana-Champaign, Urbana, IL
Gang Li , University of Illinois at Urbana-Champaign, Urbana, IL
pp. 474-477
Session 7C: Circuit-Level Analog CAD

Analog circuit sizing based on formal methods using affine arithmetic (Abstract)

Lars Hedrich , University of Hanover, Hannover, Germany
Erich Barke , University of Hanover, Hannover, Germany
Andreas Lemke , University of Hanover, Hannover, Germany
pp. 486-489

SiSMA: a statistical simulator for mismatch analysis of MOS ICs (Abstract)

P. Crippa , University of Ancona, Via Brecce Bianche, Ancona, Italy
S. Orcioni , University of Ancona, Via Brecce Bianche, Ancona, Italy
C. Turchetti , University of Ancona, Via Brecce Bianche, Ancona, Italy
L. Signoracci , University of Ancona, Via Brecce Bianche, Ancona, Italy
M. Alessandrini , University of Ancona, Via Brecce Bianche, Ancona, Italy
G. Biagetti , University of Ancona, Via Brecce Bianche, Ancona, Italy
pp. 490-496

Efficient solution space exploration based on segment trees in analog placement with symmetry constraints (Abstract)

Karthik Krishnamoorthy , University of Illinois at Chicago
Sarat C. Maruvada , University of Illinois at Chicago
Florin Balasa , University of Illinois at Chicago
pp. 497-502
Session 7D: Physical Effects in Deep Sub Micron Technology

Post global routing RLC crosstalk budgeting (Abstract)

Jun Chen , University of Wisconsin, Madison, WI
Lei He , University of Wisconsin, Madison, WI
James Ma , University of Wisconsin, Madison, WI
Jinjun Xiong , University of Wisconsin, Madison, WI
pp. 504-509

A technology-independent CAD tool for ESD protection device extraction: ESDExtractor (Abstract)

Q. Wu , Illinois Institute of Technology, Chicago, IL
Albert. Z. Wang , Illinois Institute of Technology, Chicago, IL
H. G. Feng , Illinois Institute of Technology, Chicago, IL
X. K. Guan , Illinois Institute of Technology, Chicago, IL
G. Chen , Illinois Institute of Technology, Chicago, IL
R. Y. Zhan , Illinois Institute of Technology, Chicago, IL
pp. 510-513

On mask layout partitioning for electron projection lithography (Abstract)

Xiaoping Tang , Silicon Perspective, a Cadence Company, San Jose, CA
Ronggang Yu , University of Texas at Austin, Austin, TX
D. F. Wong , University of Illinois at Urbana-Champaign, Urbana, IL
Ruiqi Tian , Motorola Inc., Austin, TX
pp. 514-518
Session 8A: Verification at the Switch, Gate, and RT Levels

High capacity and automatic functional extraction tool for industrial VLSI circuit designs (Abstract)

Ziyad Hanna , Design Technology, Intel Corporation
Shy Shyman , Design Technology, Intel Corporation
Sasha Novakovsky , Design Technology, Intel Corporation
pp. 520-525

Combinational equivalence checking through function transformation (Abstract)

In-Ho Moon , Synopsys, Inc.
James H. Kukula , Synopsys, Inc.
Thomas R. Shiple , Synopsys, Inc.
Hee Hwan Kwak , Synopsys, Inc.
pp. 526-533

GSTE Through A Case Study (Abstract)

Jin Yang , Strategic CAD Labs, Intel Corp.
Amit Goel , ECE, Carnegie-Mellon University
pp. 534-541
Session 8B: New Trends in Logic Synthesis

Whirlpool PLAs: a regular logic structure and their synthesis (Abstract)

Robert K. Brayton , University of California, Berkeley
Fan Mo , University of California, Berkeley
pp. 543-550

Metrics for structural logic synthesis (Abstract)

Andrew Sullivan , IBM Technology Group, Hopewell Junction, NY
William Dougherty , IBM Technology Group, Hopewell Junction, NY
Prabhakar Kudva , IBM TJ Watson Research Center, Yorktown Heights
pp. 551-556

Simplification of non-deterministic multi-valued networks (Abstract)

Robert Brayton , University of California, Berkeley, CA
Alan Mishchenko , Portland State University, Portland, OR
pp. 557-562
Session 8C: Memory Issues in High-Level Synthesis

High-level synthesis of distributed logic-memory architectures (Abstract)

Anand Raghunathan , NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Srivaths Ravi , NEC USA, Princeton, NJ
Chao Huang , Princeton University, Princeton, NJ
pp. 564-571

An energy-conscious algorithm for memory port allocation (Abstract)

Lakshmikantam Chitturi , Teradyne, Inc., San Jose, CA
Preeti Ranjan Panda , Indian Institute of Technology, Delhi Hauz Khas, New Delhi, India
pp. 572-576

Energy efficient address assignment through minimized memory row switching (Abstract)

Peter Y. K. Cheung , Imperial College of Science, Technology and Medicine, London, United Kingdom
Thomas J. W. Clarke , Imperial College of Science, Technology and Medicine, London, United Kingdom
Sambuddhi Hettiaratchi , Imperial College of Science, Technology and Medicine, London, United Kingdom
pp. 577-581
Session 8D: Noise Effects on Circuit Operation

Refining switching window by time slots for crosstalk noise calculation (Abstract)

Kurt Keutzer , U.C. Berkeley, Berkeley, CA
Yuji Kukimoto , Cadence Design System Inc., San Jose, CA
Pinhong Chen , U.C. Berkeley, Berkeley, CA & Cadence Design System Inc., San Jose, CA
pp. 583-586

Noise propagation and failure criteria for VLSI designs (Abstract)

R. Panda , Motorola
S. Sirichotiyakul , Sun Microsystems
C. Oh , Motorola
R. Levy , Motorola
A. Grinshpon , Motorola
M. Becer , Motorola
D. Blaauw , University of Michigan
V. Zolotov , Motorola
pp. 587-594

Efficient crosstalk noise modeling using aggressor and tree reductions (Abstract)

Pinaki Mazumder , The University of Michigan, Ann Arbor, MI
David Blaauw , The University of Michigan, Ann Arbor, MI
Li Ding , The University of Michigan, Ann Arbor, MI
pp. 595-600
Session 9A: Low Level Aware Behavioral Synthesis

Bit-level scheduling of heterogeneous behavioural specifications (Abstract)

J. M. Mend?as , Universidad Complutense de Madrid Avda. Complutense s/n, Madrid (SPAIN)
R. Hermida , Universidad Complutense de Madrid Avda. Complutense s/n, Madrid (SPAIN)
M. C. Molina , Universidad Complutense de Madrid Avda. Complutense s/n, Madrid (SPAIN)
pp. 602-608

Coupling-aware high-level interconnect synthesis for low power (Abstract)

Ki-Wook Kim , Incorporation, Cupertino, CA
Taewhan Kim , Advanced Information Technology Research Center, KAIST, Korea
Chun-Gi Lyuh , Advanced Information Technology Research Center, KAIST, Korea
pp. 609-613

Layout-driven resource sharing in high-level synthesis (Abstract)

Taewhan Kim , Korea Advanced Institute of Science and Technology, Taejon, Korea
Jae-hoon Kim , Korea Advanced Institute of Science and Technology, Taejon, Korea
Junhyung Um , Korea Advanced Institute of Science and Technology, Taejon, Korea
pp. 614-618
Session 9B: Advances in Timing Analysis Accuracy

A delay metric for RC circuits based on the Weibull distribution (Abstract)

Chandramouli Kashyap , IBM Austin, Austin, TX
Charles J. Alpert , IBM Austin, Austin, TX
Frank Liu , IBM Austin, Austin, TX
pp. 620-624

WTA: waveform-based timing analysis for deep submicron circuits (Abstract)

Carl Sechen , University of Washington, Seattle, WA
Larry McMurchie , University of Washington, Seattle, WA
pp. 625-631

General framework for removal of clock network pessimism (Abstract)

Paul Frain , Synopsys, Inc., Dublin, Ireland
Jindrich Zejda , Synopsys, Inc., Mountain View, CA
pp. 632-639
Session 9C: Customization of Embedded System Architecture

Synthesis of custom processors based on extensible platforms (Abstract)

Anand Raghunathan , C&C Research Labs, NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Srivaths Ravi , C&C Research Labs, NEC USA, Princeton, NJ
Fei Sun , Princeton University, Princeton, NJ
pp. 641-648

Efficient instruction encoding for automatic instruction set design of configurable ASIPs (Abstract)

Kiyoung Choi , Seoul National University, Seoul, South KOREA
Nikil Dutt , Univ. of California, Irvine Irvine, CA
Jong-eun Lee , Univ. of California, Irvine, Irvine, CA
pp. 649-654

Synthesis of customized loop caches for core-based embedded systems (Abstract)

Frank Vahid , University of California, Riverside
Susan Cotterell , University of California, Riverside
pp. 655-662

A hierarchical modeling framework for on-chip communication architectures (Abstract)

Sharad Malik , Princeton University, Princeton, NJ
Xinping Zhu , Princeton University, Princeton, NJ
pp. 663-671
Session 9D: Advances in Combinational Synthesis

A new enhanced SPFD rewiring algorithm (Abstract)

Wangning Long , Aplus Design Technologies, Inc.
Jason Cong , UCLA
pp. 672-678

Topologically constrained logic synthesis (Abstract)

Alan Mishchenko , Portland State University, Portland, OR
Robert K. Brayton , University of California at Berkeley, Berkeley, CA
Subarnarekha Sinha , University of California at Berkeley, Berkeley, CA
pp. 679-686

Resynthesis of multi-level circuits under tight constraints using symbolic optimization (Abstract)

Karem A. Sakallah , University of Michigan, Ann Arbor, MI
Victor N. Kravets , IBM TJ Watson Research center, Yorktown Heights, NY
pp. 687-693

Folding of logic functions and its application to look up table compaction (Abstract)

Takashi Horiyama , Kyoto University, Kyoto, Japan
Masaki Nakanishi , Information Science, Nara Institute of Science and Technology, Takayama, Japan
Hirotsugu Kajihara , Information Science, Nara Institute of Science and Technology, Takayama, Japan
Shinji Kimura , Waseda University, 2-2 Hibikino 808-0135, Japan
pp. 694-697
Session 10A: System-Level Performance and Power Modeling and Optimization

Schedulability analysis of multiprocessor real-time applications with stochastic task execution times (Abstract)

Petru Eles , Linkoping University, Sweden
Zebo Peng , Linkoping University, Sweden
Sorin Manolache , Linkoping University, Sweden
pp. 699-706

Battery-aware power management based on Markovian decision processes (Abstract)

Massoud Pedram , University of Southern California
Peng Rong , University of Southern California
pp. 707-713

Leakage power modeling and reduction with data retention (Abstract)

Lei He , UCLA, CA
Joseph M. Basile , Intel Corporation, Santa Clara, CA
Weiping Liao , UCLA, CA
pp. 714-719
Session 10B: Advances in Dynamic Voltage Scheduling

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads (Abstract)

Trevor Mudge , University of Michigan, Ann Arbor
Krisztian Flautner , ARM Limited, Cambridge, UK
David Blaauw , University of Michigan, Ann Arbor
Steven M. Martin , University of Michigan, Ann Arbor
pp. 721-725

A realistic variable voltage scheduling model for real-time applications (Abstract)

Xiaobo Sharon Hu , University of Notre Dame, Notre Dame, IN
Gang Quan , University of South Carolina, Columbia, SC
Bren Mochocki , University of Notre Dame, Notre Dame, IN
pp. 726-731

Frame-based dynamic voltage and frequency scaling for a MPEG decoder (Abstract)

Massoud Pedram , University of Southern California, Los Angeles, CA
Wei-Chung Cheng , University of Southern California, Los Angeles, CA
Karthik Dantu , University of Southern California, Los Angeles, CA
Kihwan Choi , University of Southern California, Los Angeles, CA
pp. 732-737
Session 10C: Techniques in Placement

Congestion minimization during placement without estimation (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
Bo Hu , University of California, Santa Barbara, CA
pp. 739-745

Free space management for cut-based placement (Abstract)

Paul G. Villarrubia , IBM Corporation, Austin, TX
Gi-Joon Nam , IBM Corporation, Austin, TX
Charles J. Alpert , IBM Corporation, Austin, TX
pp. 746-751

Incremental placement for layout driven optimizations on FPGAs (Abstract)

Stephen D. Brown , University of Toronto, Toronto, Ontario, Canada
Deshanand P. Singh , University of Toronto, Toronto, Ontario, Canada
pp. 752-759
Session 10D: Model Order Reduction

Robust and passive model order reduction for circuits containing susceptance elements (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Hui Zheng , Carnegie Mellon University, Pittsburgh, PA
pp. 761-766

Optimization based passive constrained fitting (Abstract)

Joel R. Phillips , Cadence Design Systems, San Jose, CA
L. Miguel Silveira , IST - Technical University of Lisbon, Lisboa, Portugal
Carlos P. Coelho , IST - Technical University of Lisbon, Lisboa, Portugal
pp. 775-780
Session 11A: Embedded Tutorial: SAT & ATPG: Boolean Engines for Formal Hardware Verification

SAT and ATPG: Boolean engines for formal hardware verification (Abstract)

Wolfgang Kunz , University of Kaiserslautern, Germany
Armin Biere , ETH, Z?rich, Switzerland
pp. 782-785

ATPG-based logic synthesis: an overview (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA
Chih-Wei Jim Chang , Cadence Design Systems, Inc., San Jose, CA
pp. 786-789
Session 11B: Embbeded Tutorial: The A to Z of SoCs

The A to Z of SoCs (Abstract)

Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 791-798

Author Index (PDF)

pp. 799-802
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