The Community for Technology Leaders
Computer-Aided Design, International Conference on (2001)
San Jose, California
Nov. 4, 2001 to Nov. 8, 2001
ISSN: 1092-3152
ISBN: 0-7803-7247-6
TABLE OF CONTENTS

Foreword (PDF)

pp. iii

Reviewers (PDF)

pp. xiv

Keynote (PDF)

pp. xxii
Session 1A: Dynamic Verification

Static Scheduling of Multi-Domain Memories For Functional Verification (Abstract)

Russell Tessier , University of Massachusetts, Amherst
Charles Selvidge , IKOS Systems Inc., Waltham, MA
Murali Kudlugi , IKOS Systems Inc., Waltham, MA
pp. 2

A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor Systems (Abstract)

Craig Barner , Compaq Computer Corporation
David Asher , Compaq Computer Corporation
Carl Ramey , Compaq Computer Corporation
Scott Taylor , Compaq Computer Corporation
pp. 10

Predicting the Performance of Synchronous Discrete Event Simulation Systems (Abstract)

Moon Jung Chung , Michigan State University
Jinsheng Xu , Michigan State University
pp. 18
Session 1B: System-Level Exploration and Design

System-level Exploration for Pareto-optimal Configurations in Parameterized Systems-on-a-chip (Abstract)

Frank Vahid , University of California, Riverside
Tony Givargis , University of California, Irvine
J?rg Henkel , C&C Research Laboratories, NEC USA, Princeton, NJ
pp. 25

System Level Design with Spade: an M-JPEG Case Study (Abstract)

Ed Deprette , Leiden Institute of Advanced, The Netherlands
Todor Stefanov , Leiden Institute of Advanced, The Netherlands
Pieter van der Wolf , Philips Research Laboratories, The Netherlands
Paul Lieverse , Delft University of Technology, The Netherlands
pp. 31

NetBench: A Benchmarking Suite for Network Processors (Abstract)

Wendong Hu , University of California, Los Angeles
Gokhan Memik , University of California, Los Angeles
William H. Mangione-Smith , University of California, Los Angeles
pp. 39
Session 1C: Interconnect Planning

Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion (Abstract)

Amir H. Ajami , Univ. of Southern California, Los Angeles
Kaustav Banerjee , Stanford University, CA
Massoud Pedram , Univ. of Southern California, Los Angeles
pp. 44

A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints (Abstract)

Hua Xiang , University of Texas at Austin, TX
Xiaoping Tang , University of Texas at Austin, TX
D. F. Wong , University of Texas at Austin, TX
Ruiqi Tian , University of Texas at Austin, TX
pp. 49

Bus Encoding to Prevent Crosstalk Delay (Abstract)

Bret Victor , University of California, Berkeley
Kurt Keutzer , University of California, Berkeley
pp. 57
Session 1D: Analog Macromodeling

Behavioral Modeling of Analog Circuits by Wavelet Collocation Method (Abstract)

Xieting Ling , Fudan University, Shanghai, China
Xuan Zeng , Fudan University, Shanghai, China
Xin Li , Fudan University, Shanghai, China
Dian Zhou , University of Texas at Dallas, Richardson, TX
pp. 65

Simulation-based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing (Abstract)

Georges Gielen , Katholieke Universiteit Leuven (Belgium)
Walter Daems , Katholieke Universiteit Leuven (Belgium)
Willy Sansen , Katholieke Universiteit Leuven (Belgium)
pp. 70
Session 3A: Sequential Synthesis

Sequential SPFDs (Abstract)

Subarnarekha Sinha , University of California at Berkeley
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA
Robert K. Brayton , University of California at Berkeley
pp. 84

On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits (Abstract)

Jos? Alberto Espejo , University Carlos III of Madrid
Luis Entrena , University Carlos III of Madrid
Enrique San Mill? , University Carlos III of Madrid
pp. 91

Placement Driven Retiming with a Coupled Edge Timing Model (Abstract)

Wolfgang Kunz , University of Frankfurt/Main, Germany
Ingmar Neumann , University of Frankfurt/Main, Germany
pp. 95

Solution of Parallel Language Equations for Logic Synthesis (Abstract)

Nina Yevtushenko , Tomsk State University, Russia
Robert K. Brayton , Univ. of California, Berkeley
Alex Petrenko , CRIM, Montreal, CAN
Tiziano Villa , Via di S.Pantaleo, Italy
Alberto L. Sangiovanni-Vincentelli , Univ. of California, Berkeley
pp. 103
Session 3B: Compiler Techniques in System Level Design

CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors (Abstract)

Margarida F. Jacome , The University of Texas at Austin
Cagdas Akturan , The University of Texas at Austin
pp. 112

Software-assisted Cache Replacement Mechanisms for Embedded Systems (Abstract)

Larry Rudolph , Massachusetts Institute of Technology, Cambridge
Daniel Engels , Massachusetts Institute of Technology, Cambridge
Srinivas Devadas , Massachusetts Institute of Technology, Cambridge
Prabhat Jain , Massachusetts Institute of Technology, Cambridge
pp. 119

Instruction Generation for Hybrid Reconfigurable Systems (Abstract)

Elaheh Bozorgzadeh , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
Ryan Kastner , University of California, Los Angeles
Seda Ogrenci-Memik , University of California, Los Angeles
pp. 127
Session 3C: Routing Architecture and Techniques for FPGAs

Interconnect Resource-Aware Placement for Hierarchical FPGAs (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Ganapathy Parthasarathy , University of California, Santa Barbara
Amit Singh , University of California, Santa Barbara
pp. 132

A Router for Symmetrical FPGAs based on Exact Routing Density Evaluation (Abstract)

Chong-Min Kyung , KAIST, Taejon, Korea
Taewhan Kim , KAIST, Taejon, Korea
Nak-Woong Eum , Electronics & Telecom. Research Institute, Taejon Korea
pp. 137

A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs (Abstract)

Shantanu Dutt , University of Illinois-Chicago
Vinay Verma , University of Illinois-Chicago
pp. 144
Session 3D: Interconnect Performance and Reliability Optimization

Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques (Abstract)

Wayne Dai , Univ. of California at Santa Cruz
Jun Gu , Hong Kong Univ. of Science and Technology, Hong Kong
Xiaohai Wu , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
C. K. Cheng , Univ. of California at San Diego
pp. 153

Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets (Abstract)

Amit Mehrotra , University of Illinois at Urbana-Champaign
Kaustav Banerjee , Stanford University, CA
pp. 158
Session 4A: Circuit Structure in Formal Verification

Min-Area Retiming on Flexible Circuit Structures (Abstract)

Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA
Jason Baumgartner , IBM Enterprise Systems Group, Austin, TX
pp. 176

Verification of Integer Multipliers on the Arithmetic Bit Level (Abstract)

Wolfgang Kunz , University of Frankfurt/Main, Germany
Dominik Stoffel , University of Frankfurt/Main, Germany
pp. 183

Induction-based Gate-level Verification of Multipliers (Abstract)

Ying-Tsai Chang , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 190
Session 4B: System Level Power and Performance Modeling

An Assembly-Level Execution-Time Model for Pipelined Architectures (Abstract)

D. Sciuto , Politecnico di Milano, Italy
V. Trianni , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
C. Brandolese , Politecnico di Milano, Italy
F. Salice , Politecnico di Milano, Italy
G. Beltrame , CEFRIEL, Milano, Italy
pp. 195

Improving Memory Energy Using Access Pattern Classification (Abstract)

Mahmut Kandemir , Pennsylvania State University, PA
Ugur Sezer , University of Wisconsin, Madison
Victor Delaluz , Pennsylvania State University, PA
pp. 201

System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels (Abstract)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Amit Nandi , Carnegie Mellon University, Pittsburgh, PA
Luciano Lavagno , Universita di' Udine, Italy
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
pp. 207
Session 4C: Topics in Physical Synthesis

Congestion Aware Layout Driven Logic Synthesis (Abstract)

Thomas Kutzschebauch , IBM TJ Watson Research Center, Yorktown Heights, NY
Leon Stok , IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 216

Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement (Abstract)

Sunil P. Khatri , University of Colorado, Boulder
Wilsin Gosti , University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley
pp. 224

An Algorithm for Simultaneous Pin Assignment and Routing (Abstract)

D. F. Wong , University of Texas at Austin, TX
Hua Xiang , University of Texas at Austin, TX
Xiaoping Tang , University of Texas at Austin, TX
pp. 232
Session 4D: Model Order Reduction

Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect (Abstract)

Alberto Sangiovanni-Vincentelli , Univ. of California, Berkeley
Jacob White , Massachusetts Institute of Technology
Luca Daniel , University of California, Berkeley
pp. 240

A Convex Programming Approach to Positive Real Rational Approximation (Abstract)

Joel R. Phillips , Cadence Design Systems, San Jose, CA
Carlos P. Coelho , IST/Technical University of Lisbon, Lisboa, Portugal
L. Miguel Silveira , IST/Technical University of Lisbon, Lisboa, Portugal
pp. 245
Session 5A: Embedded Tutorial: Embedded Software and Systems

Low Power System Scheduling and Synthesis (Abstract)

Niraj K. Jha , Princeton University, NJ
pp. 259

Internal Design Representations for Embedded Systems (PDF)

Lothar Thiele , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 264

Optimisation problems for dynamic concurrent task-based systems (Abstract)

P. Marchal , IMEC, Leuven, Belgium
C. Wong , IMEC, Leuven, Belgium
P. Yang , IMEC, Leuven, Belgium
D. Verkest , IMEC, Leuven, Belgium
pp. 265
Session 5B: Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design

CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design (Abstract)

Domine Leenaerts , Philips Research, The Netherlands
Georges Gielen , Katholieke Universiteit Leuven, Belgium
Rob A. Rutenbar , Carnegie Mellon University, U.S.A
pp. 270
Session 6A: BDDs and SAT

Partition-Based Decision Heuristics for Image Computation using SAT and BDDs (Abstract)

Zijiang Yang , CCRL, NEC USA
Pranav Ashar , CCRL, NEC USA
Lintao Zhang , Princeton University
Sharad Malik , Princeton University
Aarti Gupta , CCRL, NEC USA
pp. 286

Non-linear Quantification Scheduling in Image Computation (Abstract)

Edmund M. Clarke , Carnegie Mellon University, Pittsburgh, PA
Tom Shiple , Synopsys Inc., Beverton, OR
Helmut Veith , TU Vienna, Austria
Pankaj Chauhan , Carnegie Mellon University, Pittsburgh, PA
Jim Kukula , Synopsys Inc., Beverton, OR
Somesh Jha , University of Wisconsin, Madison, WI
Dong Wang , Carnegie Mellon University, Pittsburgh, PA
pp. 293
Session 6B: Convergence of Abstractions in High-Level Synthesis

Symbolic Algebra and Timing Driven Data-flow Synthesis (Abstract)

Giovanni De Micheli , Stanford University, CA
Armita Peymandoust , Stanford University, CA
pp. 300

Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Anoop Iyer , Carnegie Mellon University, Pittsburgh, PA
pp. 306

A System for Synthesizing Optimized FPGA Hardware from MATLAB? (Abstract)

Alok Choudhary , Northwestern University
Prith Banerjee , Northwestern University
Anshuman Nayak , Mach Design Systems, Inc.
Malay Haldar , Mach Design Systems, Inc.
pp. 314

Behavior-to-Placed RTL Synthesis with Performance-Driven Placement (Abstract)

Jinhwan Jeon , GCT Research, Inc., Seoul, Korea
Kiyoung Choi , Seoul National University, Korea
Jinyong Jung , Seoul National University, Korea
Daehong Kim , Seoul National University, Korea
Sunghyun Lee , Seoul National University, Korea
pp. 320
Session 6C: Signal Integrity and Clock Design

Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering (Abstract)

James D. Z. Ma , University of Wisconsin, Madison
Lei He , University of Wisconsin, Madison
pp. 327

Hybrid Structured Clock Network Construction (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Haihua Su , University of Minnesota, Minneapolis
pp. 333

CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic (Abstract)

Yonghee Im , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 337
Session 6D: Analog Synthesis

The Sizing Rules Method for Analog Integrated Circuit Design (Abstract)

H. Graeb , Technical University of Munich
S. Zizala , Infineon Technologies, Munich
J. Eckmueller , Infineon Technologies, Munich
K. Antreich , Technical University of Munich
pp. 343

ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits (Abstract)

James R. Hellums , Texas Instruments Incorporated, Dallas, TX
Rodney Phelps , Carnegie Mellon University, Pittsburgh, PA
Michael J. Krasnicki , Texas Instruments Incorporated, Dallas, TX
Mark McClung , Texas Instruments Incorporated, Dallas, TX
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
L. Richard Carley , Carnegie Mellon University, Pittsburgh, PA
pp. 350

A Layout-aware Synthesis Methodology for RF Circuits (Abstract)

M. Steyaert , Katholieke Universiteit Leuven, Belgium
P. Vancorenland , Katholieke Universiteit Leuven, Belgium
G. Van der Plas , Katholieke Universiteit Leuven, Belgium
W. Sansen , Katholieke Universiteit Leuven, Belgium
G. Gielen , Katholieke Universiteit Leuven, Belgium
pp. 358
Session 7A: Manufacturing Test: Stuck-at to Crosstalk

On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits (Abstract)

Kohei Miyase , Kyushu Institute of Technology, Japan
Seiji Kajihara , Kyushu Institute of Technology, Japan
pp. 364

REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , Purdue University , West Lafayette, IN
Chen Wang , University of Iowa, Iowa City
pp. 370

Crosstalk Fault Detection by Dynamic Idd (Abstract)

Seonki Kim , University of Minnesota, Minneapolis
Bapiraju Vinnakota , University of Minnesota, Minneapolis
Xiaoyun Sun , University of Minnesota, Minneapolis
pp. 375
Session 7B: Architecture Oriented Scheduling

Color Permutation: an Iterative Algorithm for Memory Packing (Abstract)

Edward S. Rogers Sr. , University of Toronto, Ontario
Jianwen Zhu , University of Toronto, Ontario
pp. 380

Constraint Satisfaction for Relative Location Assignment and Scheduling (Abstract)

Carlos Alba-Pinto , Eindhoven University of Technology
Jochen Jess , Eindhoven University of Technology
Bart Mesman , Philips Research Laboratories and Eindhoven Embedded Systems Institute
pp. 384

A Super-Scheduler for Embedded Reconfigurable Systems (Abstract)

E. Bozorgzadeh , University of California, Los Angeles
M. Sarrafzadeh , University of California, Los Angeles
S. Ogrenci Memik , University of California, Los Angeles
R. Kastner , University of California, Los Angeles
pp. 391
Session 7C: New Techniques in Routing

A Force-Directed Maze Router (Abstract)

Fan Mo , University of California at Berkeley
Abdallah Tabbara , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
pp. 404

Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control (Abstract)

Ion Mandoiu , UCSD, La Jolla, CA
Charles Alpert , IBM Corporation, Austin, TX
Andrew B. Kahng , UCSD, La Jolla, CA
Bao Liu , UCSD, La Jolla, CA
Alexander Zelikovsky , Georgia State University, Atlanta, GA
pp. 408
Session 7D: Issues in Substrate Coupling

Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation (Abstract)

Joe Kanapka , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 417

Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate (Abstract)

Minqing Liu , University of California, Santa Cruz
Wayne W.-M. Dai , University of California, Santa Cruz
Tiejun Yu , Cadence Design Systems
pp. 424

Simulation Approaches for Strongly Coupled Interconnect Systems (Abstract)

L. Miguel Silveira , IST/Technical Univ. Lisbon
Joel R. Phillips , Cadence Design Systems
pp. 430
Session 8A: Combinational Optimization

BOOM - a Heuristic Boolean Minimizer (Abstract)

Jan Hlavicka , Czech Technical University
Petr Fiser , Czech Technical University
pp. 439

Faster SAT and Smaller BDDs via Common Function Structure (Abstract)

Igor L. Markov , University of Michigan
Fadi A. Aloul , University of Michigan
Karem A. Sakallah , University of Michigan
pp. 443

Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits (Abstract)

Rupesh S. Shelar , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 449

A Probabilistic Constructive Approach To Optimization Problems (Abstract)

Farinaz Koushanfar , University of California, Berkeley
Jennifer L. Wong , University of California, Los Angeles
Seapahn Meguerdichian , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 453
Session 8B: Real Time Scheduling and Performance Analysis

Energy Efficient Real-Time Scheduling (Abstract)

Amit Sinha , Massachusetts Institute of Technology, Cambridge
Anantha P. Chandrakasan , Massachusetts Institute of Technology, Cambridge
pp. 458

Efficient Performance Estimation for General Real-Time Task Systems (Abstract)

Hongchao (Stephanie) Liu , University of Notre Dame, IN
Xiaobo (Sharon) Hu , University of Notre Dame, IN
pp. 464

STARS in VCC: complementing simulation with worst-case analysis (Abstract)

Felice Balarin , Cadence Berkeley Labs, Berkeley, CA
pp. 471
Session 8C: Power Analysis

Multigrid-like Technique for Power Grid Analysis (Abstract)

Farid N. Najm , University of Toronto
Joseph N. Kozhaya , University of Illinois, Urbana
Sani R. Nassif , IBM Austin Research Labs
pp. 480

Power-delay Modeling of Dynamic CMOS Gates for Circuit Optimization (Abstract)

J. L. Rossello , Balearic Islands University, Palma de Mallorca, Spain
Jaume Segura , Balearic Islands University, Palma de Mallorca, Spain
pp. 494
Session 8D: Timing and Noise Analysis

On the signal bounding problem in Timing analysis (Abstract)

Jin-Fuw Lee , IBM T. J. Watson Research Center, Yorktown Heights, NY
Jeffery Soreff , IBM Fishkill, Hopewell Junction, NY
D. L. Ostapko , IBM T. J. Watson Research Center, Yorktown Heights, NY
C. K. Wong , The Chinese Univ. of Hong Kong, Shatin
pp. 507

False-Noise Analysis using Logic Implications (Abstract)

Supamas Sirichotiyakul , Motorola Inc. Austin, TX
David Blaauw , University of Michigan
Chanhee Oh , Motorola Inc. Austin, TX
Sergey Gavrilov , MicroStyle - Moscow, Russia
Vladimir Zolotov , Motorola Inc. Austin, TX
Alexey Glebov , MicroStyle - Moscow, Russia
pp. 515
Session 9A: System Level Test and Reliability

The Design and Optimization of SOC Test Solutions (Abstract)

Gunnar Carlsson , Ericsson
Zebo Peng , Link?pings Universitet, Sweden
Erik Larsson , Link?pings Universitet, Sweden
pp. 523

Accurate CMOS Bridge Fault Modeling With Neural Network-Based VHDL Saboteurs (Abstract)

C?me Rozon , Royal Military College of Canada, Kingston, Ontario
Don Shaw , Gennum Corporation, Burlington, Ontario
Dhamin Al-Khalili , Royal Military College of Canada, Kingston, Ontario
pp. 531

Algorithm Level Re-Computing -- A Register Transfer Level Concurrent Error Detection Technique (Abstract)

Ramesh Karri , Polytechnic University, Brooklyn, NY
Kaijie Wu , Polytechnic University, Brooklyn, NY
pp. 537
Session 9B: Power Issues in High Level Synthesis

Transient Power Management Through High Level Synthesis (Abstract)

Srivaths Ravi , NEC USA, Princeton, NJ
Ganesh Lakshminarayana , NEC USA, Princeton, NJ
Anand Raghunathan , NEC USA, Princeton, NJ
Vijay Raghunathan , University of California, Los Angeles
pp. 545

An Integrated Data Path Optimization for Low Power Based on Network Flow Method (Abstract)

Taewhan Kim , Korea Advanced Institute of Science & Technology, Taejon
C. L. Liu , National Tsing Hua Univ., Hsinchu, Taiwan
Chun-Gi Lyuh , Korea Advanced Institute of Science & Technology, Taejon
pp. 553

What is the Limit of Energy Saving by Dynamic Voltage Scaling? (Abstract)

Gang Qu , University of Maryland, College Park
pp. 560
Session 9C: Advances in Placement

Local Search for Final Placement in VLSI Design (Abstract)

David Pisinger , University of Copenhagen, Denmark
Oluf Faroe , University of Copenhagen, Denmark
Martin Zachariasen , University of Copenhagen, Denmark
pp. 565

Congestion Reduction During Placement Based on Integer Programming (Abstract)

Majid Sarrafzadeh , University of California, Los Angeles
Xiaojian Yang , University of California, Los Angeles
Ryan Kastner , University of California, Los Angeles
pp. 573

Direct Transistor-Level Layout for Digital Blocks (Abstract)

Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
Prakash Gopalakrishnan , Carnegie Mellon University, Pittsburgh, Pennsylvania
pp. 577
Session 9D: Interconnect Analysis and Extraction

Model Reduction of Variable-Geometry Interconnects Using Variational Spectrally-Weighted Balanced Truncation (Abstract)

Payam Heydari , University of California, Irvine
Massoud Pedram , University of Southern California, Los Angeles
pp. 586

Improving the Robustness of a Surface Integral Formulation for Wideband Impendance Extraction of 3D Structures (Abstract)

Ben Song , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
Jingfang Huang , University of North Carolina, Chapel Hill
Zhenhai Zhu , Massachusetts Institute of Technology, Cambridge
pp. 592

Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits (Abstract)

Steven C. Chan , Cadence Design Systems, Inc.
K. L. Shepard , Columbia University, New York
pp. 598
Session 10A: Don't Care Optimization and Boolean Matching

Single-Pass Redundancy Addition And Removal (Abstract)

Chih-Wei (Jim) Chang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 606

Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries (Abstract)

Carl Sechen , University of Washington, Seattle, WA
Jovanka Ciric , Synplicity Inc., Sunnyvale, CA
pp. 610

Compatible Observability Don't Cares Revisited (Abstract)

R. K. Brayton , University of California, Berkeley
pp. 618
Session 10B: Power Saving Techniques for Embedded Processors

A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using the Machine Description Language LISA (Abstract)

Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen, Germany
Andreas Hoffmann , Integrated Signal Processing Systems, RWTH Aachen, Germany
Oliver Schliebusch , Integrated Signal Processing Systems, RWTH Aachen, Germany
Achim Nohl , Integrated Signal Processing Systems, RWTH Aachen, Germany
Gunnar Braun , Integrated Signal Processing Systems, RWTH Aachen, Germany
Oliver Wahlen , Integrated Signal Processing Systems, RWTH Aachen, Germany
pp. 625

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding (Abstract)

Mahesh Mehendale , Texas Instruments India Ltd., Bangalore, India
R. Govindarajan , Indian Institute of Science, Bangalore, India
Subash G Chandar , Texas Instruments India Ltd., Bangalore, India
pp. 631

I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency (Abstract)

Sri Parameswaran , The University of New South Wales, Kensington
J? Henkel , NEC USA Inc., Princeton, NJ
pp. 635
Session 10C: Embedded Tutorial: IC Power Distribution Challenges

IC Power Distribution Challenges (Abstract)

Sudhakar Bobba , Sun Microsystems, Inc.
Kathirgamar Aingaran , Afara Websystems
Dean Liu , Sun Microsystems, Inc.
Tyler Thorp , Sun Microsystems, Inc.
pp. 643

Challenges in Power-Ground Integrity (Abstract)

Shen Lin , Apache Design Solutions, Inc., Palo Alto, CA
Norman Chang , Apache Design Solutions, Inc., Palo Alto, CA
pp. 651
Session 11A: Panel: Automatic Hierarchical Design: Fantasy or Reality?

Author Index (PDF)

pp. 657
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