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Computer-Aided Design, International Conference on (2000)
San Jose, California
Nov. 5, 2000 to Nov. 9, 2000
ISSN: 1092-3152
ISBN: 0-7803-6445-7
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. iii

Reviewers (PDF)

pp. xvii

Keynote (PDF)

pp. xxi
Session 1A: Floorplanning and Partitioning

Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan (Abstract)

Chung-Kuan Cheng , University of California, San Diego
Xianlong Hong , Tsinghua University, Beijing, China
Jun Gu , University of Hong Kong
Sheqin Dong , Tsinghua University, Beijing, China
Jiangchun Gu , Tsinghua University, Beijing, China
Gang Huang , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
pp. 8

Modeling Non-Slicing Floorplans with Binary Trees (Abstract)

Florin Balasa , University of Illinois at Chicago
pp. 13

On Mismatches Between Incremental Optimizers and Instance Perturbations in Physical Design Tools (Abstract)

Stefanus Mantik , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 17
Session 1B: High Level Simulation

Event Driven Simulation Without Loops or Conditionals (Abstract)

Peter M. Maurer , Univ. of South Florida, Tampa
pp. 23

A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis (Abstract)

Taewhan Kim , KAIST, Korea
Gernot Koch , Synopsys Inc., Mountain View, CA
Reiner Genevriere , Synopsys Inc., Mountain View, CA
pp. 33
Session 1C: Methods for DSP Synthesis and Debugging

Symbolic Debugging Scheme for Optimized Hardware and Software (Abstract)

Darko Kirovski , Microsoft Research, Redmond, WA
Farinaz Koushanfar , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 40

Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering (Abstract)

Francky Catthoor , IMEC, Leuven, Belgium, also at Katholieke Universiteit Leuven
Per Gunnar Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway
Einar J. Aas , Norwegian University of Science and Technology, Trondheim, Norway
pp. 44

FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders (Abstract)

Hansoo Kim , Korea Advanced Institute of Science and Technology, Korea
In-Cheol Park , Korea Advanced Institute of Science and Technology, Korea
Hyeong-Ju Kang , Korea Advanced Institute of Science and Technology, Korea
pp. 51
Session 1D: Issues in Timing Estimation

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design (Abstract)

Yu Cao , UC Berkeley, USA
Chenming Hu , UC Berkeley, USA
Dirk Stroobandt , Ghent University, Belgium
Andrew B. Kahng , UCLA, USA
Xuejue Huang , UC Berkeley, USA
Sudhakar Muddu , Silicon Graphics, Inc., USA
Dennis Sylvester , Synopsys, Inc., USA
pp. 56

Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits (Abstract)

Pinhong Chen , University of California, Berkeley
Chenming Hu , University of California, Berkeley
Michael Orshansky , University of California, Berkeley
Kurt Keutzer , University of California, Berkeley
Linda Milor , eSilicon Corporation, Berkeley, CA
pp. 62

Miller Factor for Gate-Level Coupling Delay Calculation (Abstract)

Kurt Keutzer , U. C. Berkeley
Desmond A. Kirkpatrick , Intel Corp., Hillsboro, OR
Pinhong Chen , U. C. Berkeley
pp. 68
Session 2A: Embedded Tutorial

Challenges and Opportunities in Broadband and Wireless Communication Designs (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Jan M. Rabaey , University of California, Berkeley
Suet-Fei Li , University of California, Berkeley
Farinaz Koushanfar , University of California, Los Angeles
Tim Tuan , University of California, Berkeley
pp. 76
Session 2B: Embedded Tutorial

Challenges in Physical Chip Design (Abstract)

Ralph H. J. M. Otten , Eindhoven University of Technology, The Netherlands
Paul Stravers , Philips Research, The Netherlands
pp. 84
Session 3A: Topics in Routing

General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs (Abstract)

Yu-Liang Wu , Chinese University of Hong Kong
Jiping Liu , University of Lethbridge
Hongbing Fan , University of Victoria
pp. 93

A Timing-constrained Algorithm for Simultaneous Global Routing of Multiple Nets (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Jiang Hu , University of Minnesota, Minneapolis
pp. 99

Provably Good Global Buffering Using an Available Buffer Block Plan (Abstract)

Alexander Zelikovsky , Georgia State University, Atlanta
Andrew B. Kahng , UCLA Department of Computer Science, Los Angeles
Feodor F. Dragan , UCLA Department of Computer Science, Los Angeles
Ion Mandoiu , Georgia Institute of Technology, Atlanta
Sudhakar Muddu , Silicon Graphics, Inc., Mountain View, CA
pp. 104

Predictable Routing (Abstract)

Elaheh Bozorgzadeh , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Ryan Kastner , Northwestern University, Evanston, IL
pp. 110
Session 3B: Partial Verification Techniques

Smart Simulation Using Collaborative Formal and Simulation Engines (Abstract)

Kevin Harer , Advanced Technology Group, Synopsys Inc.
Valeria Bertacco , Advanced Technology Group, Synopsys Inc.
Jerry Taylor , Advanced Technology Group, Synopsys Inc.
Pei-Hsin Ho , Advanced Technology Group, Synopsys Inc.
James Kukula , Advanced Technology Group, Synopsys Inc.
Jiang Long , Advanced Technology Group, Synopsys Inc.
Thomas Shiple , Advanced Technology Group, Synopsys Inc.
Robert Damiano , Advanced Technology Group, Synopsys Inc.
pp. 120

Simulation Coverage Enhancement Using Test Stimulus Transformation (Abstract)

C. Norris Ip , Cadence Berkeley Labs, California
pp. 127
Session 3C: Scheduling and Compilation for Embedded Systems

Dynamic Response Time Optimization for SDF Graphs (Abstract)

Jan Uerpmann , TU Braunschweig
Rolf Ernst , TU Braunschweig
Dirk Ziegenbein , TU Braunschweig
pp. 135
Session 3D: Inductance and Full-Wave Analysis

Full-chip, three-dimensional, shapes-based RLC extraction (Abstract)

Yu Zheng , Columbia University, New York, NY
D. Sitaram , Columbia University, New York, NY
K. L. Shepard , Columbia University, New York, NY
pp. 142

How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K (Abstract)

Hao Ji , UC Santa Cruz CE Dept.
Anirudh Devgan , IBM Microelectronics, Austin, TX
Wayne Dai , UC Santa Cruz CE Dept.
pp. 150

Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling (Abstract)

Tae-Woo Lee , University of Wisconsin-Madison
Charlie C.-P. Chen , University of Wisconsin-Madison
Narayanan Murugesan , University of Wisconsin-Madison
Susan C. Hagness , University of Wisconsin-Madison
pp. 156
Session 4A: Placement I

Mongrel: Hybrid Techniques for Standard Cell Placement (Abstract)

John Lillis , University of Illinois at Chicago
Sung-Woo Hur , University of Illinois at Chicago
pp. 165

A Force-Directed Macro-Cell Placer (Abstract)

Fan Mo , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
Abdallah Tabbara , University of California, Berkeley
pp. 177
Session 4B: High-Level Design Tools for Analog Circuits

Verification of Delta-Sigma Converters Using Adaptive Regression Modeling (Abstract)

Jeongjin Roh , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
Suresh Seshadri , The University of Texas at Austin
pp. 182

DAISY: A Simulation-Based High-Level Synthesis Tool for \Delta\Sigma Modulators (Abstract)

K. Francken , Katholieke Universiteit Leuven
P. Vancorenland , Katholieke Universiteit Leuven
G. Gielen , Katholieke Universiteit Leuven
pp. 188

ACTIF: A high-level power estimation tool for Analog Continuous-Time Filters (Abstract)

Erik Lauwers , Katholieke Universiteit Leuven
Georges Gielen , Katholieke Universiteit Leuven
pp. 193
Session 4C: Delay Budgeting and Distribution

Potential Slack: An Effective Metric of Combinational Circuit Performance (Abstract)

Chunhong Chen , Northwestern University, Evanston, IL
Xiaojian Yang , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
pp. 198

Delay Budgeting for A Timing-Closure-Driven Design Method (Abstract)

Allen C.-H. Wu , Tsing Hua University, Hsinchu, Taiwan
Chien-Chu Kuo , Tsing Hua University, Hsinchu, Taiwan
pp. 202

Stochastic Wire-Length and Delay Distributions of 3-Dimensional Circuits (Abstract)

David B. Janes , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Rongtian Zhang , Purdue University, West Lafayette, IN
pp. 208
Session 4D: Interconnect Analysis

Hierarchical Interconnect Circuit Models (Abstract)

Satrajit Gupta , Carnegie Mellon University, Pittsburgh, PA
Michael Beattie , Carnegie Mellon University, Pittsburgh, PA
Lawrence Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 215

Hurwitz Stable Reduced Order Modeling for RLC Interconnect Trees (Abstract)

Robert J. Carragher , Fujitsu Laboratories of America
Chung-Kuan Cheng , U.C. San Diego
Xiaodong Yang , U.C. San Diego
Walter H. Ku , U.C. San Diego
pp. 222

An "Effective" Capacitance Based Delay Metric for RC Interconnect (Abstract)

Chandramouli V. Kashyap , IBM Corp., Austin, TX
Charles J. Alpert , IBM Corp., Austin, TX
Anirudh Devgan , IBM Corp., Austin, TX
pp. 229
Session 5A: Embedded Tutorial

Incremental CAD (Abstract)

Sharad Malik , Princeton University, NJ
Olivier Coudert , Monterey Design Systems, Sunnyvale, CA
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Jason Cong , University of California, Los Angeles
pp. 236
Session 5B: Embedded Tutorial

Decomposing Refinement Proofs using Assume-Guarantee Reasoning (Abstract)

Shaz Qadeer , Compaq Systems Research Center
Sriram K. Rajamani , Microsoft Research
Thomas A. Henzinger , University of California, Berkeley
pp. 245
Session 6A: Placement II

Effective Partition-Driven Placement with Simultaneous Level Processing and Global Net Views (Abstract)

Shantanu Dutt , University of Illinois-Chicago
Ke Zhong , University of Illinois-Chicago
pp. 254

Dragon2000: Standard-Cell Placement Tool for Large Industry Circuits (Abstract)

Xiaojian Yang , Northwestern University, Evan ston, IL
Majid Sarrafzadeh , Northwestern University, Evan ston, IL
Maogang Wang , Northwestern University, Evan ston, IL
pp. 260

Data Path Placement with Regularity (Abstract)

Terry Tao Ye , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
pp. 264
Session 6B: Analog and RF Simulation

Noise Analysis of Phase-Locked Loops (Abstract)

Amit Mehrotra , Univerity of Illinois at Urbana-Champaign
pp. 277

Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices (Abstract)

David Long , Bell Laboratories, Murray Hill, New Jersey
Alper Demir , Bell Laboratories, Murray Hill, New Jersey
Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, New Jersey
pp. 283
Session 6C: Markovian Analysis and Asynchronous Circuits

Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm (Abstract)

Peter A. Beerel , University of Southern California, Los Angeles
Sangyun Kim , University of Southern California, Los Angeles
pp. 296
Session 6D: Low Power Interconnect Modeling and Optimization

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design (Abstract)

Kwang-Hyun Baek , Univ. of Illinois at Urbana-Champaign, USA
C. L. Liu , National Tsing Hua University, Taiwan
Naresh Shanbhag , Univ. of Illinois at Urbana-Champaign, USA
Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign, USA
Ki-Wook Kim , Univ. of Illinois at Urbana-Champaign, USA
pp. 318

Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Sub-Micron Technologies (Abstract)

Paul P. Sotiriadis , Massachusetts Institute of Technology, Cambridge
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge
pp. 322
Session 7A: Panel

Why Doesn't EDA Get Enough Respect? (PDF)

A. Richard Newton , Univ. of California, Berkeley
pp. 329
Session 8A: Static Timing Analysis

Slope Propagation in Static Timing Analysis (Abstract)

Rajendran Panda , Motorola Inc. Austin, TX
Chanhee Oh , Motorola Inc. Austin, TX
David Blaauw , Motorola Inc. Austin, TX
Vladimir Zolotov , Motorola Inc. Austin, TX
Savithri Sundareswaran , Motorola India Electronics Ltd., Bangalore, India
pp. 338

Transistor-Level Timing Analysis Using Embedded Simulation (Abstract)

Pawan Kulshreshtha , Cadence Design Systems Inc., San Jose, CA
Mohammad Mortazavi , Cadence Design Systems Inc., San Jose, CA
Hakan Yalcin , Cadence Design Systems Inc., San Jose, CA
Cyrus Bamji , Canesta Inc., Santa Clara, CA
Robert Palermo , Cadence Design Systems Inc., San Jose, CA
pp. 344
Session 8B: Embedded Systems Power Management and Validation

Latency Effects of System Level Power Management Algorithms (Abstract)

Sandy Irani , University of California, Irvine
Rajesh Gupta , University of California, Irvine
Dinesh Ramanathan , University of California, Irvine
pp. 350

Power Optimization of Real-Time Embedded Systems on Variable Speed Processors (Abstract)

Kiyoung Choi , Seoul National University, Korea
Youngsoo Shin , University of Tokyo, Japan
Takayasu Sakurai , University of Tokyo, Japan
pp. 365

A Data Flow Fault Coverage Metric For Validation of Behavioral HDL Descriptions (Abstract)

Ian G. Harris , University of Massachusetts, Amherst
Qiushuang Zhang , University of Massachusetts, Amherst
pp. 369
Session 8C: Advances in Layout and Synthesis

Simultaneous Gate Sizing and Fanout Optimization (Abstract)

Wei Chen , University of Southern California, Los Angeles
Cheng-Ta Hsieh , Verplex Systems, Inc., Milpitas, CA
Massoud Pedram , University of Southern California, Los Angeles
pp. 374

Layout-driven Area-constrained Timing Optimization by Net Buffering (Abstract)

Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 379

Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation (Abstract)

Shih-Chieh Chang , National Chung Cheng University, Chiayi, Taiwan
Ching-Hwa Cheng , National Chung Cheng University, Chiayi, Taiwan
Jinn-Shyan Wang , National Chung Cheng University, Chiayi, Taiwan
Wen-Ben Jone , National Chung Cheng University, Chiayi, Taiwan
Shin-De Li , National Chung Cheng University, Chiayi, Taiwan
pp. 387
Session 8D: Embedded Tutorial

Test of Future System-on-Chips (Abstract)

Yervant Zorian , LogicVision Inc., San Jose, CA
Michael J. Rodgers , Intel Corp., Santa Clara, CA
Sujit Dey , University of California at San Diego, La Jolla
pp. 392
Session 9A: Noise and Performance Issues in Routing

UST/DME: A Clock Tree Router For General Skew Constraints (Abstract)

Chung-Wen Albert Tsao , Ultima Interconnect Technology, Sunnyvale, CA
Cheng-Kok Koh , ECE, Purdue University, West Lafayette, IN
pp. 400

A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise (Abstract)

Guoan Zhong , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
pp. 406
Session 9B: Communication Architectures Design and Analysis

Latency-Guided On-Chip Bus Network Design (Abstract)

Darko Kirovski , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
Seapahn Meguerdichian , University of California, Los Angeles
Milenko Drinic , University of California, Los Angeles
pp. 420

Efficient Exploration of the SoC Communication Architecture Design Space (Abstract)

Sujit Dey , UC San Diego
Anand Raghunathan , NEC USA C&C Research Labs, Princeton, NJ
Kanishka Lahiri , UC San Diego
pp. 424

MIST: An Algorithm for Memory Miss Traffic Management (Abstract)

Alex Nicolau , University of California, Irvine
Peter Grun , University of California, Irvine
Nikil Dutt , University of California, Irvine
pp. 431
Session 9C: Performance Driven Logic Synthesis

Regularity Driven Logic Synthesis (Abstract)

Thomas Kutzschebauch , IBM TJ Watson Research Center, Yorktown Heights, NY
Leon Stok , IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 439

Timing Driven Gate Duplication: Complexity Issues and Algorithms (Abstract)

Ankur Srivastava , Northwestern University, Evanston, Illinois
Ryan Kastner , Northwestern University, Evanston, Illinois
Majid Sarrafzadeh , Northwestern University, Evanston, Illinois
pp. 447

An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays (Abstract)

Arlindo L. Oliveira , Cadence European Labs./IST-INESC, Lisboa, Portugal
Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 451
Session 9D: New Approaches to At-Speed BIST and Diagnosis

Improving the proportion of At-Speed Tests in Scan BIST (Abstract)

Y. Huang , University of Iowa, Iowa City
I. Pomeranz , Purdue University, West Lafayette, IN
S. M. Reddy , University of Iowa, Iowa City
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 459

Fast Test Application Technique Without Fast Scan Clocks (Abstract)

Bapiraju Vinnakota , University of Minnesota, Minneapolis
Seonki Kim , University of Minnesota, Minneapolis
pp. 464

Error Catch and Analysis for Semiconductor Memories Using March Tests (Abstract)

Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Hsinchu, Taiwan
Chi-Feng Wu , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 468

Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures (Abstract)

Ian Harris , University of Massachusetts at Amherst
Russell Tessier , University of Massachusetts at Amherst
pp. 472
Session 10A: Power Analysis and Optimization

Simulation and Optimization of the Power Distribution Network in VLSI Circuits (Abstract)

S. Bobba , University of Illinois at Urbana-Champaign
I. N. Hajj , University of Illinois at Urbana-Champaign
G. Bai , University of Illinois at Urbana-Champaign
pp. 481

Frequency Domain Analysis of Switching Noise on Power Supply Network (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Shiyou Zhao , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
pp. 487

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara
Jing-Jia Liou , University of California, Santa Barbara
Yi-Min Jiang , Synopsys Inc., Mountain View, CA
Angela Krstic , University of California, Santa Barbara
pp. 493
Session 10B: VLIW Exploration and Design Synthesis

Power Exploration for Embedded VLIW Architectures (Abstract)

Vittorio Zaccaria , Politecnico di Milano, Italy
Cristina Silvano , Politecnico di Milano, Italy
Mariagiovanna Sami , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
pp. 498

Exploring Performance Tradoffs for Clustered VLIW ASIPs (Abstract)

Gustavo de Veciana , University of Texas, Austin, TX
Margarida F. Jacome , University of Texas, Austin, TX
Viktor Lapinskii , University of Texas, Austin, TX
pp. 504

Synthesis of Operation-Centric Hardware Descriptions (Abstract)

James C. Hoe , Carnegie Mellon University
Arvind , Massachusetts Institute of Technology
pp. 511
Session 10C: Flexibility in Logic Synthesis

Don?t Cares and Multi-Valued Logic Network Minimization (Abstract)

Robert K. Brayton , University of California, Berkeley
Yunjian Jiang , University of California, Berkeley
pp. 520

Generalized Symmetries in Boolean Functions (Abstract)

Karem A. Sakallah , University of Michigan, Ann Arbor
Victor N. Kravets , University of Michigan, Ann Arbor
pp. 526

Wire Reconnections Based on Implication Flow Graph (Abstract)

Shih-Chieh Chang , National Chung-Cheng University, Chia-Yi, Taiwan
He-Zhe Yu , National Chung-Cheng University, Chia-Yi, Taiwan
Zhong-Zhen Wu , National Chung-Cheng University, Chia-Yi, Taiwan
pp. 533
Session 10D: Digital and Analog Test Generation

Deterministic Test Pattern Generation Techniques for Sequential Circuits (Abstract)

Ilker Hamzaoglu , Motorola Labs, Schaumburg, IL
Janak H. Patel , University of Illinois, Urbana, IL
pp. 538

Simulation Based Test Generation for Scan Designs (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , University of Iowa, Iowa City
pp. 544

Test Generation for Acyclic Sequential Circuits with Hold Registers (Abstract)

Chiiho Sano , Nara Institute of Science and Technology, Japan
Debesh Kumar Das , Jadavpur University, India
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Tomoo Inoue , Hiroshima City University, Japan
Takahiro Mihara , Mitsubishi Electronic Control Software Corporation, Japan
pp. 550

A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits (Abstract)

V. Gloeckel , Technical University of Munich
M. Pronath , Technical University of Munich
H. Graeb , Technical University of Munich
pp. 557

Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
Sudip Chakrabarti , Georgia Institute of Technology, Atlanta
pp. 562
Session 11A: Embedded Tutorial
Session 11B: Embedded Tutorial

Design-Manufacturing Interface for 0.13 micron and Below (PDF)

Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh & PDF Solutions, Inc., San Jose, CA
pp. 575

Author Index (PDF)

pp. 576
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