The Community for Technology Leaders
Computer-Aided Design, International Conference on (1999)
San Jose, CA
Nov. 7, 1999 to Nov. 11, 1999
ISSN: 1092-3152
ISBN: 0-7803-5832-5
TABLE OF CONTENTS

Foreword (PDF)

pp. iii

Reviewers (PDF)

pp. xvii
Session 1A: Sequential and Datapath Optimization

Marsh:Min-Area Retiming with Setup and Hold Constraints (Abstract)

Vijay Sundararajan , University of Minnesota, Minneapolis
Keshab K. Parhi , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 2

OPTIMISTA: State Minimization of Asynchronous FSMs for Optimum Output Logic (Abstract)

Robert M. Fuhrer , Columbia University, New York, NY
Steven M. Nowick , Columbia University, New York, NY
pp. 7

Bit-level Arithmetic Optimization for Carry-Save Additions (Abstract)

Alan N. Willson, Jr. , University of California, Los Angeles
Zhan Yu , University of California, Los Angeles
Kei-Yong Khoo , University of California, Los Angeles
pp. 14
Session 1B: Placement I

Attractor-Repeller Approach for Global Placement (Abstract)

Hussein Etawil , University of Waterloo, Ontario
Anthony Vannelli , University of Waterloo, Ontario
Shawki Areibi , University of Waterloo, Ontario
pp. 20

Cell Replication and Redundancy Elimination During Placement for Cycle Time Optimization (Abstract)

Dominik Stoffel , J.W.G. University Frankfurt a.M, Germany
Hendrik Hartje , University of Potsdam, Germany
Wolfgang Kunz , J.W.G. University Frankfurt a.M, Germany
Ingmar Neumann , J.W.G. University Frankfurt a.M, Germany
pp. 25

Concurrent Logic Restructuring and Placement for Timing Closure (Abstract)

Jinan Lou , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Wei Chen , University of Southern California, Los Angeles
pp. 31
Session 1C: BDDs in Formal Verification

Implicit Enumeration of Strongly Connected Components (Abstract)

Peter A. Beerel , University of Southern California, Los Angeles
Aiguo Xie , University of Southern California, Los Angeles
pp. 37

Least Fixpoint Approximations for Reachability Analysis (Abstract)

Fabio Somenzi , University of Colorado at Boulder
James Kukula , Advanced Technology Group, Synopsys Inc.
In-Ho Moon , University of Colorado at Boulder
Tom Shiple , Advanced Technology Group, Synopsys Inc.
pp. 41

Lazy Group Sifting for Efficient Symbolic State Traversal of FSMs (Abstract)

Fabio Somenzi , University of Colorado, Boulder
Hiroyuki Higuchi , Fujitsu Laboratories Ltd., Kawasaki, Japan
pp. 45

Efficient Manipulation Algorithms for Linearly Transformed BDDs (Abstract)

Wolfgang G?nther , Albert-Ludwigs-University, Germany
Rolf Drechsler , Albert-Ludwigs-University, Germany
pp. 50
Session 1D: Analog and Mixed-Signal

Noise Analysis of Non-Autonomous Radio Frequency Circuits (Abstract)

Amit Mehrotra , University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley
pp. 55

New Methods for Speeding up Computation of Newton Updates in Harmonic Balance (Abstract)

M. Gourary , IPPM, Russian Academy of Sciences, Moscow
S. Rusakov , IPPM, Russian Academy of Sciences, Moscow
M. Zharov , IPPM, Russian Academy of Sciences, Moscow
S. Ulyanov , IPPM, Russian Academy of Sciences, Moscow
K. Gullapalli , Motorola Inc., Austin, Texas
B. Mulvaney , Motorola Inc., Austin, Texas
pp. 61

Design and optimization of LC oscillators (Abstract)

Maria del Mar Hershenson , Stanford University
Stephen P. Boyd , Stanford University
Sunderarajan S. Mohan , Stanford University
Ali Hajimiri , California Institue of Technology
Thomas H. Lee , Stanford University
pp. 65

Modeling and Simulation of the Interference due to Digital Switching in Mixed-Signal ICs (Abstract)

Peter Feldmann , Bell Laboratories, Murray Hill, New Jersey
Alper Demir , Bell Laboratories, Murray Hill, New Jersey
pp. 70
Session 2A: Power Optimization

Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages (Abstract)

Majid Sarrafzadeh , Northwestern University, Evanston, IL
Chunhong Chen , Northwestern University, Evanston, IL
pp. 76

A Novel Design Methodology for High Performance and Low Power Digital Filters (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Khurram Muhammad , Texas Instruments, Dallas, TX
pp. 80

A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits (Abstract)

Shanq-Jang Ruan , National Taiwan University, Taipei
Rung-Ji Shang , National Taiwan University, Taipei
Xian-Jun Huang , National Taiwan University, Taipei
Feipei Lai , National Taiwan University, Taipei
Shyh-Jong Chen , National Taiwan University, Taipei
pp. 84
Session 2B: Placement II

AKORD: Transistor Level and Mixed Transistor/Gate Level Placement Tool for Digital Data Paths (Abstract)

Tatjana Serdar , University of Washington, Seattle
Carl Sechen , University of Washington, Seattle
pp. 91

Analytical Approach to Custom Datapath Design (Abstract)

Maciej Ciesielski , University of Massachusetts, Amherst
Serkan Askar , University of Massachusetts, Amherst
pp. 98

An Integrated Algorithm for Combined Placement and Libraryless Technology Mapping (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Yanbin Jiang , Cadence Design Systems, Inc., San Jose, CA
pp. 102
Session 2C: Domino- and ATPG-Based Logic Synthesis

Timing-driven Partitioning for Two-Phase Domino and Mixed Static/Domino Implementations (Abstract)

Min Zhao , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
pp. 107

Implication Graph based Domino Logic Synthesis (Abstract)

C. L. Liu , National Tsing Hua University
Sung-Mo Kang , University of Illinois at Urbana-Champaign
Ki-Wook Kim , University of Illinois at Urbana-Champaign
pp. 111

Synthesis for Multiple Input Wires Replacement of a Gate for Wiring Consideration (Abstract)

Jung-Cheng Chuang , National Chung-Cheng University, Jay-Yi, Taiwan
Zhong-Zhen Wu , National Chung-Cheng University, Jay-Yi, Taiwan
Shih-Chieh Chang , National Chung-Cheng University, Jay-Yi, Taiwan
pp. 115
Session 2D: Electrical and Thermal Analysis

Transient Sensitivity Computation for Transistor Level Analysis and Tuning (Abstract)

Peter O'Brien , IBM EDA, Austin, TX
David Winston , IBM EDA, Hopewell Junction, NY
Tuyen V. Nguyen , IBM Austin Research Laboratory, TX
pp. 120

An Efficient Method for Hot-spot Identification in ULSI Circuits (Abstract)

Yi-Kan Cheng , Motorola Inc., Austin, TX
Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign
pp. 124

A Scalable Substrate Noise Coupling Model for Mixed-Signal ICs (Abstract)

Anil Samavedam , Silicon Laboratories Inc., Austin, TX
Terri Fiez , Oregon State University, Corvallis, OR
Karti Mayaram , Washington State University, Pullman, WA
pp. 128

Towards True Crosstalk Noise Analysis (Abstract)

Pinhong Chen , Univ. of California at Berkeley
Kurt Keutzer , Univ. of California at Berkeley
pp. 132
Session 3A: Automatic Test Pattern Generation

SAT Based ATPG Using Fast Justification and Propagation in the Implication Graph (Abstract)

Andreas Ganz , Technical University of Munich, Germany
Paul Tafertshofer , Technical University of Munich, Germany
pp. 139

Techniques for Improving the Efficiency of Sequential Circuit Test Generation (Abstract)

Xijiang Lin , Mentor Graphics Corporation, Wilsonville, OR
Irith Pomeranz , University of Iowa, Iowa City
pp. 147

Concurrent D-Algorithm on Reconfigurable Hardware (Abstract)

Fatih Kocan , Case Western Reserve University, Cleveland, Ohio
Daniel G. Saab , Case Western Reserve University, Cleveland, Ohio
pp. 152
Session 3B: Routing

A New Heuristic for Rectilinear Steiner Trees (Abstract)

Ion I. Mandoiu , Georgia Institute of Technology, Atlanta
Vijay V. Vazirani , Georgia Institute of Technology, Atlanta
Joseph L. Ganley , Simplex Solutions, Inc., Sunnyvale, CA
pp. 157

An Implicit Connection Graph Maze Routing Algorithm for ECO Routing (Abstract)

Kei-Yong Khoo , UCLA, Los Angeles
Jason Cong , UCLA, Los Angeles
Jie Fang , UCLA, Los Angeles
pp. 163

The Associative-Skew Clock Routing Problem (Abstract)

Andrew B. Kahng , UCLA Department of Computer Science, Los Angeles, CA
Gang Qu , UCLA Department of Computer Science, Los Angeles, CA
Yu Chen , UCLA Department of Computer Science, Los Angeles, CA
Alexander Zelikovsky , Georgia State University, Atlanta
pp. 168
Session 3C: Logic-Level Performance Optimization

Optimal P/N Width Ratio Selection for Standard Cell Libraries (Abstract)

David S. Kung , IBM T. J. Watson Research Center, Yorktown Heights, NY
Ruchir Puri , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 178

Performance Optimization Under Rise and Fall Parameters (Abstract)

Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 185

Performance Optimization Using Separator Sets (Abstract)

Yutaka Tamiya , Fujitsu Laboratories Ltd., Kawasaki, Japan
pp. 191

Factoring Logic Functions Using Graph Partitioning (Abstract)

Martin C. Golumbic , Bar Ilan University, Israel
Aviad Mintz , Bar Ilan University, Israel
pp. 195
Session 3D: Practical Issues in Order Reduction

TICER: Realizable Reduction of Extracted RC Circuits (Abstract)

Bernard N. Sheehan , Mentor Graphics, Wilsonville, OR
pp. 200

Realizable Reduction for RC Interconnect Circuits (Abstract)

Peter R. O'Brien , IBM Corporation, Austin, TX
Anirudh Devgan , IBM Corporation, Austin, TX
pp. 204

RLC Interconnect Delay Estimation via Moments of Amplitude and Phase Response (Abstract)

Xiaodong Yang , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Walter H. Ku , University of California, San Diego
pp. 208

Practical Considerations For Passive Reduction of RLC Circuits (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Altan Odabasioglu , Monterey Design Systems, Inc., Sunnyvale, CA
Mustafa Celik , Monterey Design Systems, Inc., Sunnyvale, CA
pp. 214
Session 4A: Embedded Tutorial
Session 4B: Embedded Tutorial

Interconnect Parasitic Extraction in the Digital IC Design Methodology (Abstract)

Mattan Kamon , Microcosm Technologies, Inc, Cambridge, Ma
Steve McCormick , Sapphire Design Automation, Santa Clara, CA
Ken Shepard , Columbia University, New York, NY
pp. 223
Session 5A: Timing Optimization

Cycle Time and Slack Optimization for VLSI-Chips (Abstract)

J. Schietke , University of Bonn, Germany
J. Vygen , University of Bonn, Germany
B. Korte , University of Bonn, Germany
C. Albrecht , University of Bonn, Germany
pp. 232

Clock Skew Scheduling for Improved Reliability via Quadratic Programming (Abstract)

Eby G. Friedman , University of Rochester, New York
Ivan S. Kourtev , University of Pittsburgh, Pennsylvania
pp. 239

Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation (Abstract)

Andrew R. Conn , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 244
Session 5B: Compilation Techniques for Embedded Systems

Function Inlining under Code Size Constraints for Embedded Processors (Abstract)

Peter Marwedel , University of Dortmund, Germany
Rainer Leupers , University of Dortmund, Germany
pp. 253

Function Unit Specialization through Code Analysis (Abstract)

William H. Mangione-Smith , UCLA, Los Angeles, CA
Daniel Benyamin , UCLA, Los Angeles, CA
pp. 257

Lower Bound on Latency for VLIW ASIP Datapaths (Abstract)

Margarida F. Jacome , University of Texas, Austin
Gustavo de Veciana , University of Texas, Austin
pp. 261
Session 5C: High Level Power Exploration

Interface and Cache Power Exploration for Core-Based Embedded System Design (Abstract)

J? Henkel , NEC USA, Princeton, NJ
Tony D. Givargis , University of California, Riverside
Frank Vahid , University of California, Riverside
pp. 270

Dynamic Power Management Using Adaptive Learning Tree (Abstract)

Giovanni De Micheli , Stanford University, CA
Luca Benini , Universit? di Bologna, Italy
Eui-Young Chung , Stanford University, CA
pp. 274

Analytical Macromodeling for High-Level Power Estimation (Abstract)

Marios C. Papaefthymiou , University of Michigan, Ann Arbor
Giuseppe Bernacchia , University of Trieste, Italy
pp. 280

Parameterized RTL Power Models for Combinational Soft Macros (Abstract)

Roberto Corgnati , Politecnico di Torini, Italy
Massimo Poncino , Politecnico di Torini, Italy
Enrico Macii , Politecnico di Torini, Italy
Alessandro Bogliolo , Universit? di Bologna, Italy
pp. 284
Session 5D: Analog and Mixed Signal Test

Validation and Test Generation for Oscillatory Noise in VLSI Interconnects (Abstract)

Melvin A. Breuer , University of Southern California, Los Angeles
Arani Sinha , University of Southern California, Los Angeles
Sandeep K. Gupta , University of Southern California, Los Angeles
pp. 289

Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects (Abstract)

Yi Zhao , University of California, San Diego
Sujit Dey , University of California, San Diego
Xiaoliang Bai , University of California, San Diego
Michael Cuviello , University of California, San Diego
pp. 297

Robust Optimization Based Backtrace Method for Analog Circuits (Abstract)

Alfred V. Gomes , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
pp. 304
Session 6A: Globally Untimed Locally Timed Design

A Methodology for Correct-by-Construction Latency Insensitive Design (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
Luca P. Carloni , University of California at Berkeley
Kenneth L. McMillan , Cadence Berkeley Laboratories
Alexander Saldanha , Cadence Berkeley Laboratories
pp. 309

What is the cost of Delay Insensitivity? (Abstract)

Hiroshi Saito , Univ. of Aizu, Japan
Jordi Cortadella , Univ. Polit?cnica, Catalunya, Spain
Alexander Yakovlev , Univ. of Newcastle upon Tyne, UK
Alex Kondratyev , Univ. of Aizu, Japan
Luciano Lavagno , Univ. of Udine, Italy
pp. 316

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions (Abstract)

Ken Stevens , Strategic CAD Lab, Intel Corporation, USA
Steven M. Burns , Strategic CAD Lab, Intel Corporation, USA
Jordi Cortadella , Univ. Polit?cnica de Catalunya, Barcelona, Spain
Michael Kishinevsky , Strategic CAD Lab, Intel Corporation, USA
pp. 324

Direct Synthesis of Timed Asynchronous Circuits (Abstract)

Chris J. Myers , University of Utah, Salt Lake City
Sung Tae Jung , University of Utah, Salt Lake City
pp. 332
Session 6B: Task-Level Analysis and Synthesis

Power Minimization using System-Level Partitioning of Applications with Quality of Service Requirements (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Gang Qu , University of California, Los Angeles
pp. 343

Worst-case analysis of discrete systems (Abstract)

Felice Balarin , Cadence Berkeley Laboratories
pp. 347
Session 6C: Floorplanning and Partitioning

Integrated Floorplanning and Interconnect Planning (Abstract)

Hung-Ming Chen , University of Texas at Austin, TX
Hannah H. Yang , Intel Corporation, Hillsboro, OR
D. F. Wong , University of Texas at Austin, TX
F. Y. Young , University of Texas at Austin, TX
Hai Zhou , University of Texas at Austin, TX
Naveed Sherwani , Intel Corporation, Hillsboro, OR
pp. 354

Buffer Block Planning for Interconnect-Driven Floorplanning (Abstract)

Tianming Kong , University of California, Los Angeles
David Zhigang Pan , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 358

A Clustering- and Probability-based Approach for Time-multiplexed FPGA Partitioning (Abstract)

Guang-Ming Wu , National Chiao Tung University, Hsinchu, Taiwan
Mango Chia-Tso Chao , National Chiao Tung University, Hsinchu, Taiwan
Yao-Wen Chang , National Chiao Tung University, Hsinchu, Taiwan
Iris Hui-Ru Jiang , National Chiao Tung University, Hsinchu, Taiwan
pp. 364
Session 6D: Advances in Model Order Reduction

The Chebyshev expansion based passive model for distributed interconnect networks (Abstract)

Qingjian Yu , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
Janet M. Wang , University of California at Berkeley
pp. 370

Model Reduction for DC Solution of Large Nonlinear Circuits (Abstract)

Emad Gad , Carleton University, Ottawa, Canada
Michel Nakhla , Carleton University, Ottawa, Canada
pp. 376

Efficient Model Reduction of Interconnect via Approximate System Gramians (Abstract)

Jing-Rebecca Li , Massachusetts Institute of Technology, Cambridge
Jacob White , Massachusetts Institute of Technology, Cambridge
pp. 380
Session 7A: Core Test

A Framework for Testing Core-Based Systems-on-a-Chip (Abstract)

Niraj K. Jha , Princeton University, NJ
Ganesh Lakshminarayana , NEC USA, Inc., Princeton, NJ
Srivaths Ravi , Princeton University, NJ
pp. 385

Test Scheduling for Core-Based Systems (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
pp. 391

Partial BIST Insertion to Eliminate Data Correlation (Abstract)

Qiushuang Zhang , University of Massachusetts at Amherst
Ian Harris , University of Massachusetts at Amherst
pp. 395
Session 7B: Graph Techniques for Design Optimization

A Graph Theoretic Optimal Algorithm for Schedule Compression in Time-Multiplexed FPGA Partitioning (Abstract)

D. F. Wong , University of Texas at Austin, TX
Huiqun Liu , University of Texas at Austin, TX
pp. 400

Throughput Optimization of General Non-Linear Computations (Abstract)

Inki Hong , Synopsys Inc., Mountain View, CA
Lisa M. Guerra , Rockwell Semiconductor, Newport Beach, CA
Miodrag Potkonjak , University of California, Los Angeles
pp. 406

Optimal Allocation of Carry-Save-Adders in Arithmetic Optimization (Abstract)

Taewhan Kim , Korea Adv. Institute of Science & Technology, Taejon, Korea
Junhyung Um , Korea Adv. Institute of Science & Technology, Taejon, Korea
C. L. Liu , National Tsing Hua Univ., Hsinchu, Taiwan
pp. 410

Regularity Extraction Via Clan-Based Structural Circuit Decomposition (Abstract)

Soha Hassoun , Tufts University, Medford, MA
Carolyn McCreary , Compaq Computer Corp., Shrewsbury, MA
pp. 414
Session 7C: Interconnect

Repeater Insertion in Tree Structured Inductive Interconnect (Abstract)

Eby G. Friedman , University of Rochester, New York
Yehea I. Ismail , University of Rochester, New York
Jose L. Neves , IBM Microelectronics, East Fishkill, New York
pp. 420

Interconnect Scaling Implications for CAD (Abstract)

Hema Kapadia , Stanford University, CA
Ron Ho , Stanford University, CA
Ken Mai , Stanford University, CA
Mark Horowitz , Stanford University, CA
pp. 425

Is Wire Tapering Worthwhile? (Abstract)

Stephen T. Quay , IBM Server Group, Austin, TX
Charles J. Alpert , IBM Austin Research Laboratory, TX
Anirudh Devgan , IBM Server Group, Austin, TX
pp. 430
Session 7D: Techniques for Parasitic Extraction

Virtual Screening: A Step Towards a Sparse Partial Inductance Matrix (Abstract)

N. P. van der Meijs , Delft University of Technology
A. J. Dammers , Netherlands Institute for Metals Research and Delft University of Technology
pp. 445

A Wide Frequency Range Surface Integral Formulation for 3-D RLC Extraction (Abstract)

J. Wang , M.I.T. Cambridge, MA
J. White , M.I.T. Cambridge, MA
J. Tausch , Southern Methodist University
pp. 453
Session 8A: Embedded Tutorial
Session 8B: Embedded Tutorial
Session 9A: Test Pattern Analysis

An Approach for Improving the Levels of Compaction Achieved by Vector Omission (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City
Irith Pomeranz , University of Iowa, Iowa City
pp. 463

Deep Submicron Defect Detection with the Energy Consumption Ratio (Abstract)

Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 467

Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Pankaj Pant , Georgia Institute of Technology
pp. 471
Session 9B: Memory and Interconnect Optimization in High Level Synthesis

Memory Bank Customization and Assignment in Behavioral Synthesis (Abstract)

Preeti Ranjan Panda , Advanced Technology Group, Synopsys, Inc., Mountain View, CA
pp. 477

Memory Binding for Performance Optimization of Control-flow Intensive Behaviors (Abstract)

Kamal S. Khouri , Princeton University, NJ
Ganesh Lakshminarayana , NEC USA, Inc., Princeton, NJ
Niraj K. Jha , Princeton University, NJ
pp. 482

Improved Interconnect Sharing by Identity Operation Insertion (Abstract)

Dirk Herrmann , Technische Universit?t Braunschweig, Germany
Rolf Ernst , Technische Universit?t Braunschweig, Germany
pp. 489
Session 9C: System Verification

Formal Specification and Verification of a Dataflow Processor Array (Abstract)

Thomas A. Henzinger , University of California at Berkeley
Shaz Qadeer , University of California at Berkeley
Sriram K. Rajamani , University of California at Berkeley
Xiaojun Liu , University of California at Berkeley
pp. 494

Synchronous Equivalence for Embedded Systems: A Tool for Design Exploration (Abstract)

Harry Hsieh , University of California, Berkeley
Luciano Lavagno , Cadence Design Systems
Felice Balarin , Cadence Design Systems
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
pp. 505
Session 9D: Fanout Optimization

On The Global Fanout Optimization Problem (Abstract)

Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 511

LEOPARD: A Logical Effort-based fanout OPtimizer for ARea and Delay (Abstract)

Amir H. Ajami , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Peyman Rezvani , University of Southern California, Los Angeles
Hamid Savoj , Magma Design Automation, Inc., Cupertino, CA
pp. 516

Optimum Loading Dispersion for High-Speed Tree-Type Decision Circuitry (Abstract)

Iris Hui-Ru Jiang , National Chiao Tung University
Jie-Hong Roland Jiang , National Chiao Tung University
pp. 520
Session 10A: Timing Analysis

Symbolic Functional and Timing Verification of Transistor-Level Circuits (Abstract)

Randal E. Bryant , Carnegie Mellon University, Pittsburgh, PA
Clayton B. McDonald , Carnegie Mellon University, Pittsburgh, PA
pp. 526

Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis (Abstract)

Kenneth L. Shepard , Columbia University, New York, NY
Dae-Jin Kim , Columbia University, New York, NY
pp. 531

Functional Timing Optimization (Abstract)

Alexander Saldanha , Cadence Berkeley Laboratories
pp. 539

Timing-Safe False Path Removal for Combinational Modules (Abstract)

Yuji Kukimoto , Monterey Design Systems, Inc., Sunnyvale, CA
Robert K. Brayton , University of California, Berkeley
pp. 544
Session 10B: Concurrency in Embedded Systems

FunState-An Internal Design Representation for Codesign (Abstract)

J. Teich , University of Paderborn, Germany
K. Strehl , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
R. Ernst , Technical University of Braunschweig, Braunschweig, Germany
D. Ziegenbein , Technical University of Braunschweig, Braunschweig, Germany
L. Thiele , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 558

Fast Performance Analysis of Bus-Based System-On-Chip Communication Architectures (Abstract)

Anand Raghunathan , NEC USA C&C Research Labs, Princeton, NJ
Kanishka Lahiri , UC San Diego
Sujit Dey , UC San Diego
pp. 566
Session 10C: Semi-Formal Verification

Probabilistic State Space Search (Abstract)

Kenneth L. McMillan , Cadence Design Systems, Berkeley, CA
Robert K. Brayton , University of California at Berkeley
Andreas Kuehlmann , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 574

Improving Coverage Analysis and Test Generation for Large Designs (Abstract)

Mark A. Horowitz , Stanford University, CA
Jules P. Bergmann , Stanford University, CA
pp. 580

Modeling Design Constraints and Biasing in Simulation Using BDDs (Abstract)

Hillel Miller , Motorola Inc., Herzelia, Israel
Kurt Shultz , Motorola Inc., Austin, TX
Jun Yuan , Motorola Inc., Austin, TX
Carl Pixley , Motorola Inc., Austin, TX
Adnan Aziz , University of Texas at Austin
pp. 584
Session 10D: Intellectual Property Protection

Copyright Protection of Designs Based on Multi Source IPs (Abstract)

Ilhami Torunoglu , Cadence Design Systems, San Jose, CA
Edoardo Charbon , Cadence Design Systems, San Jose, CA
pp. 591

Localized Watermarking: Methodology and Application to Operation Scheduling (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 596

Copy Detection for Intellectual Property Protection of VLSI Designs (Abstract)

Jennifer L. Wong , UCLA Computer Science Dept., Los Angeles, CA
Miodrag Potkonjak , UCLA Computer Science Dept., Los Angeles, CA
Darko Kirovski , UCLA Computer Science Dept., Los Angeles, CA
Stefanus Mantik , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 600
Session 11A: Embedded Tutorial
Session 11B: ICCAD/ISSS Invited Papers
Session 12A: Embedded Tutorial
Session 12B: Joint ICCAD / ISSS Session

Author Index (PDF)

pp. 614
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