The Community for Technology Leaders
Computer-Aided Design, International Conference on (1998)
San Jose, California, United States
Nov. 8, 1998 to Nov. 12, 1998
ISBN: 1-58113-008-2
TABLE OF CONTENTS
Tutorial 1: Embedded Memories in systems Design - from Technology to Systems Architecture
Tutorial 2: Real-Time Operating Systems for Embedded Computing
Tutorial 3: High-Level Design Validation and Test
Tutorial 4: Interconnect in High Speed Designs: Problems, Methodologies and Tools
Panel: How Will CAD Handle Billion-Transistor Systems?
Session 1A: Topics in Circuit Simulation

Efficient Transient Electrothermal Simulation of CMOS VLSI Circuits under Electrical Overstress (Abstract)

Ching-Han Tsai , Univ. of Illinois at Urbana-Champaign
Sung-Mo Steve Kang , Univ. of Illinois at Urbana-Champaign
Tong Li , Avant! Corporation
pp. 6-11

Simulation of Coupling Capacitances using Matrix Partitioning (Abstract)

Ali Sadigh , IBM Electronic Design Automation, HopeweIl Junction, NY
Anirudh Devgan , IBM Austin Research Laboratory, Austin, TX
Tuyen V. Nguyen , IBM Austin Research Laboratory, Austin, TX
pp. 12-18

h-gamma: An RC Delay Metric Based on a Gamma Distribution Approximation of the Homogeneous Response (Abstract)

Lawrence Pileggi , Carnegie Mellon University, Pittsburgh, PA
Tao Lin , Carnegie Mellon University, Pittsburgh, PA
Emrah Acar , Carnegie Mellon University, Pittsburgh, PA
pp. 19-25
Session 1B: Layout and Logic Synthesis

Wireplanning in Logic Synthesis (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California Berkeley, CA
Amit Narayan , Monterey Design Systems, Sunnyvale, CA
Robert K. Brayton , University of California Berkeley, CA
Wilsin Gosti , University of California Berkeley, CA
pp. 26-33

Graph Matching-Based Algorithms for FPGA Segmentation Design (Abstract)

Yao-Wen Chang , National Chiao Tung University, Hsinchu, Taiwan
Jai-Ming Lin , National Chiao Tung University, Hsinchu, Taiwan
D. F. Wong , University of Texas at Austin
pp. 34-39

Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources (Abstract)

Jason Cong , University of California, Los Angeles
Songjie Xu , University of California, Los Angeles
pp. 40-44
Session 1C: Dynamic System Synthesis

Control Generation for Embedded Systems Based on Composition of Modal Processes (Abstract)

Gaetano Borriello , University of Washington, Seattle
Pai Chou , University of Washington, Seattle
Ken Hines , University of Washington, Seattle
Kurt Partidge , University of Washington, Seattle
pp. 46-53

Representation of Process Mode Correlation for Scheduling (Abstract)

D. Ziegenbein , TU Braunschweig
L. Thiele , ETH Z?
R. Ernst , TU Braunschweig
J. Teich , ETH Z?
K. Richter , TU Braunschweig
pp. 54-61

CORDS: Hardware-Software Co-Synthesis of Reconfigurable Real-Time Distributed Embedded Systems (Abstract)

Robert P. Dick , Princeton University, New Jersey
Niraj K. Jha , Princeton University, New Jersey
pp. 62-67
Session 1D: Design for Testability

Synthesis of BIST Hardware for Performance Testing of MCM Interconnections (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
Yervant Zorian , LogicVision, Inc., San Jose, CA
Rajesh Pendurkar , Georgia Institute of Technology, Atlanta
pp. 69-73

Using a Single Input to Support Multiple Scan Chains (Abstract)

Jih-Jeen Chen , Nat'l Cheng-Kung U., Tainan, Taiwan
Cheng-Hua Huang , Nat'l Cheng-Kung U., Tainan, Taiwan
Kuen-Jong Lee , Nat'l Cheng-Kung U., Tainan, Taiwan
pp. 74-78

High-level Variable Selection for Partial-Scan Implementation (Abstract)

Frank F. Hsu , University of Illinois, Urbana
Janak H. Patel , University of Illinois, Urbana
pp. 79-84
Session 2A: Reduced Order Modelling

Multipoint Moment Matching Model For Multiport Distributed Interconnect Networks (Abstract)

Janet M. Wang , University of California at Berkeley
Qingjian Yu , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
pp. 85-91

Reduced-Order Modelling of Linear Time-Varying Systems (Abstract)

Jaijeet Roychowdhury , Bell Laboratories, Murray Hill
pp. 92-95
Session 2B: Combinational Logic Synthesis

Implementation and Use of SPFDS in Optimizing Boolean Networks (Abstract)

Subarnarekha Sinha , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 103-110

Finding All Simple Disjunctive Decompositions Using Irredundant Sum-of-Products Fornls (Abstract)

Shin-ichi Minato , NTT Optical Network Systems Labs., Kanagawa, Japan
Giovanni De Micheli , Stanford University, CA
pp. 111-117

On Accelerating Pattern Matching for Technology Mapping (Abstract)

Yusuke Matsunaga , Fujitsu Laboratories Limited
pp. 118-122
Session 2C: Topics in Layout

A Performance-driven Layer Assignment Algorithm for Multiple Interconnect Trees (Abstract)

Prashant Saxena , Intel Corporation, Inc., Hillsboro, OR
C. L. Liu , National Tsing Hua University, Hsinchu, Taiwan
pp. 124-127

Optimal 2-D Cell Layout with Integrated Transistor Folding (Abstract)

John P. Hayes , University of Michigan, Ann Arbor
Avaneendra Gupta , Cadence Design Systems, Inc., San Jose, CA
pp. 128-135

Integrating Logic Retiming and Register Placement (Abstract)

Tzu-Chieh Tien , Tsing Hua University, Hsin-Chu, Taiwan
Youn-Long Lin , Tsing Hua University, Hsin-Chu, Taiwan
Yih-Chih Chou , Tsing Hua University, Hsin-Chu, Taiwan
Hsiao-Pin Su , Tsing Hua University, Hsin-Chu, Taiwan
Yu-Wen Tsay , Tsing Hua University, Hsin-Chu, Taiwan
pp. 136-139
Session 2D: Sequential Circuit Testing

Static Compaction Using Overlapped Restoration and Segment Pruning (Abstract)

Kiran B. Doreswamy , NEC USA Inc., Princeton, NJ
Srimat T. Chakradhar , NEC USA Inc., Princeton, NJ
Surendra K. Bommu , NEC USA Inc., Princeton, NJ
pp. 140-146

Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits (Abstract)

Vamsi Boppana , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
W. Kent Fuchs , Purdue University, West Lafayette, IN
pp. 147-154
Session 3A: Numerical Techniques for Simulation and Extraction

Simulation of High-Q Oscillators (Abstract)

B. J. Mulvaney , Motorola Inc., Austin, Texas
S. Rusakov , NIISAPRAN, Russian Academy of Sciences, Moscow
M. Zharov , NIISAPRAN, Russian Academy of Sciences, Moscow
M. Gourary , NIISAPRAN, Russian Academy of Sciences, Moscow
K. K. Gullapalli , Motorola Inc., Austin, Texas
S. Ulyanov , NIISAPRAN, Russian Academy of Sciences, Moscow
pp. 162-169

Phase Noise in Oscillators: DAEs and Colored Noise Souces (Abstract)

Alper Demir , Bell Laboratories, Murray Hill, New Jersey
pp. 170-177

High-Order Nystr?m Schemes for Efficient 3-D Capacitance Extraction (Abstract)

David E. Long , Lucent Technologies, Murray Hill, NJ
Sharad Kapur , Lucent Technologies, Murray Hill, NJ
pp. 178-185
Session 3B: Intellectual Property Protection

Signature Hiding Techniques for FPGA Intellectual Property Protection (Abstract)

William H. Mangione-Smith , The University of California, Los Angeles
John Lach , The University of California, Los Angeles
Miodrag Potkonjak , The University of California, Los Angeles
pp. 186-189

Analysis of Watermarking Techniques for Graph Coloring Problem (Abstract)

Miodrag Potkonjak , The University of California, Los Angeles
Gang Qu , The University of California, Los Angeles
pp. 190-193

Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions (Abstract)

Darko Kirovski , The University of California, Los Angeles
Miodrag Potkonjak , The University of California, Los Angeles
Yean-Yow Hwang , The University of California, Los Angeles
Jason Cong , The University of California, Los Angeles
pp. 194-198
Session 4A: Embedded Tutorial - Estimating Noise in RF Systems

Estimating Noise in RF Systems (Abstract)

Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, New Jersey
Alper Demir , Bell Laboratories, Murray Hill, New Jersey
pp. 199-202
Session 4B: Embedded Tutorial - Getting to the Bottom of Deep Submicron

Getting to the Bottom of Deep Submicron (Abstract)

Kurt Keutzer , University of California, Berkeley
Dennis Sylvester , University of California, Berkeley
pp. 203-211
Session 5A: Noise in Digital Systems

Determination of Worst-Case Aggressor Alignment for Delay Calculation (Abstract)

Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Paul D. Gross , Carnegie Mellon University, Pittsburgh, PA
Ravishankar Arunachalam , Carnegie Mellon University, Pittsburgh, PA
Karthik Rajagopal , Carnegie Mellon University, Pittsburgh, PA
pp. 212-219

Noise Considerations in Circuit Optimization (Abstract)

Ruud A. Haring , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Andrew R. Conn , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 220-227

Energy-Efficiency in Presence of Deep Submicron Noise (Abstract)

Rajamohana Hegde , University of Illinois at Urbana-Champaign
Naresh R. Shanbhag , University of Illinois at Urbana-Champaign
pp. 228-234
Session 5B: Pass Transistor and Domino Logic Synthesis

Symbofic Algorithms for Layout-Oriented Synthesis of Pass fiansistor Logic Circuits (Abstract)

F. Somenzi , University of Colorado, Boulder
M. Poncino , Politecnico di Torino, Italy
A. Macii , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
R. Scarsi , Politecnico di Torino, Italy
F. Ferrandi , Politecnico di Milano, Italy
pp. 235-241

Domino Logic Synthesis Using Complex Static Gates (Abstract)

Carl Sechen , University of Washington, Seattle
Gin Yee , University of Washington, Seattle
Tyler Thorp , University of Washington, Seattle
pp. 242-247

Technology Mapping for Domino Logic (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Min Zhao , University of Minnesota, Minneapolis
pp. 248-251
Session 5C: Floorplanning

Slicing Floorplans with Pre-Placed Modules (Abstract)

D. F. Wong , The University of Texas at Austin
F. Y. Young , The University of Texas at Austin
pp. 252-258

Arbitrary Rectilinear Block Packing Based on Sequence Pair (Abstract)

Maggie Zhiwei Kang , Cadence Design Systems, Inc.
Wayne Wei-Mingi Dai , University of California at Santa Cruz
pp. 259-266

The Multi-BSG: Stochmtic Approach to an Optimum Packing of Convex-Rectilinear Blocks (Abstract)

Yoji Kajitani , Tokyo Institute of Technology
Shigetoshi Nakatake , Tokyo Institute of Technology
Keishi Sakanushi , Tokyo Institute of Technology
pp. 267-274
Session 5D: Test Generation Techniques

On Primitive Fault Test Generation in Non-Scan Sequential Circuit (Abstract)

Ramesh C. Tekumalla , Intel Corporation, Hillsboro
Prem R. Menon , University of Massachusetts, Amherst
pp. 275-282

Test Set Compaction Algorithms for Combinational Circuits (Abstract)

Janak H. Patel , University of Illinois, Urbana
Ilker Hamzaoglu , University of Illinois, Urbana
pp. 283-289

A linear optimal test generation algorithm for interconnect testing (Abstract)

Chauchin Su , National Central University, Chung-Li, Taiwan
pp. 290-295
Session 6A: Analog Circuit Synthesis

GPCAD: A Tool for CMOS Op-Amp Synthesis (Abstract)

Thomas H. Lee , Stanford University, CA
Stephen P. Boyd , Stanford University, CA
Maria del Mar Hershenson , Stanford University, CA
pp. 296-303

An Efficient DC Root Solving Algorithm with Guaranteed Convergence for Analog Integrated CMOS Circuits (Abstract)

Franky Leyn , Katholieke Universiteit Leuven, Belgium
Willy Sansen , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 304-307

Efficient Analog Circuit Synthesis with simultaneous Yield and Robustness Optimization (Abstract)

Geert Debyser , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 308-311
Session 6B: Timing Optimization in Sequential Synthesis

Reencoding for Cycle-Time Minimization under Fixed Encoding Length (Abstract)

Maciej Ciesielski , University of Massachusetts, Amherst
Balakrishnan Iyer , University of Massachusetts, Amherst
pp. 312-315

Using Precomputation in Architecture and Logic Resynthesis (Abstract)

Carl Ebeling , University of Washington, Seattle
Soha Hassoun , Tufts University, Medford, MA
pp. 316-323

Lazy Transition Systems: Application to Timing Optimization of Asynchronous Circuits (Abstract)

Luciano Lavagno , Politecnico di Torino, Italy
Alex Kondratyev , The University of Aizu, Japan
Alexander Taubin , The University of Aizu, Japan
Michael Kishinevsky , Intel Corp., Hillsboro, Oregon
Alex Yakovlev , University of Newcastle upon Tyne, UK
Jordi Cortadella , Univ. Polit?cnica de Catalunya, Barcelona, Spain
pp. 324-331
Session 6C: Issues in High-Level Synthesis

A general approach for regularity extraction in datapath circuits (Abstract)

Amit Chowdhary , Intel Corporation, Santa Clara, CA
Phani Saripella , Intel Corporation, Santa Clara, CA
Sudhakar Kale , Intel Corporation, Santa Clara, CA
Rajesh Gupta , University of California, Irvine
Naresh Sehgal , Intel Corporation, Santa Clara, CA
pp. 332-339

A Quantitative Approach to Development and Validation of Synthetic Benchmarks for Behavioral Synthesis (Abstract)

Chunho Lee , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 347-351
Session 6D: Sequential Verification

Approximate Reachability Don't Cares for CTL Model Checking (Abstract)

Fabio Somenzi , University of Colorado, Boulder
Carl Pixley , Motorola Inc., Austin, TX
In-Ho Moon , University of Colorado, Boulder
Jun Yuan , Motorola Inc., Austin, TX
Jae-Young Jang , University of Colorado, Boulder
Gary D. Hachtel , University of Colorado, Boulder
pp. 351-358

Adaptive Variable Reordering for Symbolic Model Checking (Abstract)

Limor Fix , Intel Israel Ltd., Haifa
Gila Kamhi , Intel Israel Ltd., Haifa
pp. 359-365

Verification by Approximate Forward and Backward Reachability (Abstract)

Shankar G. Govindaraju , Stanford University, CA
David L. Dill , Stanford University, CA
pp. 366-370
Session 7A: Analog Test and Layout

CMOS Analog Circuit Stack Generation with Matching Constraints (Abstract)

Terri Fiez , Washington State University, Pullman
Ravindranath Naiknaware , Washington State University, Pullman
pp. 371-375

Testability Analysis and Multi-frequency ATPG for Analog Circuits and Systems (Abstract)

Seongwon Kim , University of Washington
Sam D. Huynh , University of Washington
Jinyan Zhang , University of Washington
Mani Soma , University of Washington
pp. 376-383

CONCERT: A Concurrent Transient Fault Simulator for Nonlinear Analog Circuits (Abstract)

Junwei Hou , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
pp. 384-391
Session 7B: Timing Optimization of Sequential Circuits

Waiting False Path Analysis of Sequential Logic Circuits for Performance Optimization (Abstract)

Katsumasa Watanabe , Nara Institute of Science and Technology, Japan
Kazuhiro Nakamura , Nara Institute of Science and Technology, Japan
Shinji Kimura , Nara Institute of Science and Technology, Japan
Kazuyoshi Takagi , Nara Institute of Science and Technology, Japan
pp. 392-395

On the Optimization Power of Retiming and Resynthesis Transformations (Abstract)

Rajeev K. Ranjan , Synopsys Inc., Mountain View, CA
Fabio Somenzi , University of Colorado, Boulder
Robert K. Brayton , University of California, Berkeley
Vigyan Singhal , Cadence Berkeley Labs, CA
pp. 402-407
Session 7C: Partitioning and Floorplanning

Architecture Driven Circuit Partitioning (Abstract)

Chau-Shen Chen , National Tsing Hua University, HsinChu, Taiwan
C. L. Liu , National Tsing Hua University, HsinChu, Taiwan
TingTing Hwang , National Tsing Hua University, HsinChu, Taiwan
pp. 408-411

Integrating Floorplanning In Data-Transfer Based High-Level Synthesis (Abstract)

Shantanu Tarafdar , Synopsys Inc., Mountain View, CA
Zixin Yin , Northeastern University, Boston, MA
Miriam Leeser , Northeastern University, Boston, MA
pp. 412-417

The Channeled-BSG: A Universal Floorplan for Simultaneous Place/Route with IC Applications (Abstract)

Shigetoshi Nakatake , Tokyo Institute of Technology
Keishi Sakanushi , Tokyo Institute of Technology
Masahiro Kawakita , Toshiba Corporation
Yoji Kajitani , Tokyo Institute of Technology
pp. 418-425
Session 7D: Memory and Interfaces Synthesis

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization (Abstract)

Youn-Long Lin , Tsing Hua University, Hsin-Chu, Taiwan
Yih-Chih Chou , Tsing Hua University, Hsin-Chu, Taiwan
pp. 426-429

Hardware/Software Co-Synthesis with Memory Hierarchies (Abstract)

Yanbing Li , Princeton University, NJ
Wayne Wolf , Princeton University, NJ
pp. 430-436

Communication Synthesis for Distributed Embedded Systems (Abstract)

Gaetano Borriello , University of Washington, Seattle
Ross B. Ortega , University of Washington, Bothell
pp. 437-444
Session 8A: Embedded Tutorial - Core-Based Design

Analysis of Emerging Core-Based Design Lifecycle (Abstract)

Kayhan K???k?akar , Escalade Corp., Santa Clara, CA
pp. 445-449

Core Integration: Overview and Challenges (Abstract)

Enno Wein , LSI Logic, Pleasanton, CA
pp. 450-452
Session 8B: Embedded Tutorial - Full-Chip Verification of UDSM Designs

Full-Chip Verification of UDSM Designs (Abstract)

R. Saleh , Simplex Solutions, Sunnyvale, CA
D. Overhauser , Simplex Solutions, Sunnyvale, CA
S. Taylor , CMOS Solutions, Olga, WA
pp. 453-460
Session 9A: Efficient Power Estimation

Node Sampling: a Robust RTL Power Modeling Approach (Abstract)

Luca Benini , DEIS - Universit? di Bologna - Italy
Alessandro Bogliolo , DEIS - Universit? di Bologna - Italy
pp. 461-467

Estimation of Power Sensitivity in Sequential Circuits with Power Macromodeling Application (Abstract)

Kaushik Roy , Purdue Univ., W. Lafayette, IN
Zhanping Chen , Purdue Univ., W. Lafayette, IN
Edwin K. P. Chong , Purdue Univ., W. Lafayette, IN
pp. 468-472

Power Invariant Vector Sequence Compaction (Abstract)

Ali Pinar , University of Illinois at Urbana-Champaign
C. L. Liu , National Tsing Hua University
pp. 473-476
Session 9B: Optimization Techniques

A New Algorithm for the Reduction of Incompletely Specified Finite State Machines (Abstract)

Jorge M. Pena , IST-INESC, Lisboa, Portugal
Arlindo L. Oliveira , Cadence European Labs/IST-INESC, Lisboa, Portugal
pp. 482-489

Static Power Optimization of Deep Submicron CMOS Circuits for Dual V<sub>T</sub> Technology (Abstract)

Qi Wang , University of Arizona, Tucson
Sarma B. K. Vrudhula , University of Arizona, Tucson
pp. 490-496
Session 9C: Circuit Partitioning

Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs (Abstract)

Huiqun Liu , University of Texas at Austin, TX
D. F. Wong , University of Texas at Austin, TX
pp. 497-504

On Multilevel Circuit Partitioning (Abstract)

Einar J. Aas , Norwegian University of Science and Technology
Sverre Wichlund , Alcatel Telecom Norway
pp. 505-511

Multiway Partitioning with Pairwise Movement (Abstract)

Sung Kyu Lim , UCLA Department of Computer Science, Los Angeles
Jason Cong , UCLA Department of Computer Science, Los Angeles
pp. 512-516
Session 9D: System-Level Verification

Verification of RTL Generated from Scheduled Behavior in a High-Level Synthesis Flow (Abstract)

Anand Raghunathan , C&C Research Labs, NEC USA, Princeton, NJ
Subhrajit Bhattacharya , C&C Research Labs, NEC USA, Princeton, NJ
Akira Mukaiyama , C&C Research Labs, NEC USA, Princeton, NJ
Pranav Ashar , C&C Research Labs, NEC USA, Princeton, NJ
pp. 517-524

Functional Debugging of Systems-On-Chip (Abstract)

Darko Kirovski , University of California, Los Angeles
Lisa M. Guerra , Rockwell Semiconductor Systems, Newport Beach
Miodrag Potkonjak , University of California, Los Angeles
pp. 525-528

Formal Verification of Pipeline Control Using Controlled Token Nets and Abstract Interpretation (Abstract)

Adrian J. Isles , University of California, Berkeley
Pei-Hsin Ho , Intel Corporation
Timothy Kam , Intel Corporation
pp. 529-536
Session 10A: Delay Modeling and Optimization

Proposal of a Timing Model for CMOS Logic Gates Driving a CRC \pi Load (Abstract)

Hidetoshi Onodera , Kyoto University, Sakyo-ku, Japan
Keikichi Tamaru , Kyoto University, Sakyo-ku, Japan
Akio Hirata , Kyoto University, Sakyo-ku, Japan
pp. 537-544

Gate-Size Selection for Standard Cell Libraries (Abstract)

David Kung , IBM TJ Watson Research Center, Yorktown Heights, NY
Frederik Beeftink , Delft University of Technology, The Netherlands
Leon Stok , IBM TJ Watson Research Center, Yorktown Heights, NY
Prabhakar Kudva , IBM TJ Watson Research Center, Yorktown Heights, NY
pp. 545-550

Fanout Optimization Under a Submicron Transistor-Level Delay Model (Abstract)

M. Zamboni , Politecnico di Torino, Italy
M. Pedram , Univ. of Southern California, Los Angeles
G. Piccinini , Politecnico di Torino, Italy
P. Cocchini , Politecnico di Torino, Italy
pp. 551-556
Session 10B: Combinational and Sequential Equivalence Checking

Efficient Equivalence Checking of Multi-Phase Designs Using Retiming (Abstract)

Prithviraj Banerjee , Northwestern University
Anmol Mathur , Ambit Design Systems
Gagan Hasteer , Ambit Design Systems
pp. 557-562

Robust Latch Mapping for Combinational Equivalence Checking (Abstract)

Vigyan Singhal , Cadence Berkeley Labs
Jerry R. Burch , Cadence Berkeley Labs
pp. 563-569

Tight Integration of Combinational Verification Methods (Abstract)

Jerry R. Burch , Cadence Berkeley Labs
Vigyan Singhal , Cadence Berkeley Labs
pp. 570-576
Session 10C: Scheduling in High-Level Synthesis

Removal of Memory Access Bottlenecks for Scheduling Control-Flow Intensive Behavioral Descriptions (Abstract)

Niraj K. Jha , Princeton University, NJ
Ganesh Lakshminarayana , Princeton University, NJ
Srivaths Ravi , Princeton University, NJ
pp. 577-584

Period Assignment in Multidimensional Periodic Scheduling (Abstract)

Emile H. L. Aarts , Philips Research Laboratories, The Netherlands; Endhoven University of Technology, The Netherlands
Paul C. N. van Gorp , Endhoven University of Technology, The Netherlands
Wim F. J. Verhaegh , Philips Research Laboratories, The Netherlands
pp. 585-592

Improving the Computational Performance of ILP-based Problems (Abstract)

J. Ramanujam , Louisiana State University, Baton Rouge
M. Narasimhan , Louisiana State University, Baton Rouge
pp. 593-596
Session 10D: Issues in Power Analysis and Optimization

Techniques for Energy Minimization of Communication Pipelines (Abstract)

Gang Qu , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
pp. 597-600

PowerDrive: A Fast, Canonical POWER Estimator for DRIVing synthEsis (Abstract)

Prithviraj Banerjee , Northwestern University, Evanston, IL
Sumit Roy , Ambit Design Systems, Santa Clara, CA
Harm Arts , Ambit Design Systems, Santa Clara, CA
pp. 601-606

Accurate Calculation of Bit-Level Transition Activity Using Word-Level Statistics and Entropy Function (Abstract)

A. Tatsaki , Silicon Graphics, Mountain View, CA
S. Nikolaidis , University of Thessaloniki, Greece
E. D. Kyriakis-Bitzaros , NCSR "Demokritos", Greece
pp. 607-610
Session 11A: Advances in Interconnect Optimization

Shaping a VLSI Wire to Minimize Delay Using Transmission Line Model (Abstract)

D. F. Wong , University of Texas at Austin
Youxin Gao , University of Texas at Austin
pp. 611-616

Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation (Abstract)

Chris C. N. Chu , University of Texas at Austin, TX
D. F. Wong , University of Texas at Austin, TX
Chung-Ping Chen , University of Texas at Austin, TX
pp. 617-624

A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm (Abstract)

Amir H. Salek , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Jinan Lou , University of Southern California, Los Angeles
pp. 625-630
Session 11B: Improved and Characterizing BDD Performance

Sampling Schemes for Computing OBDD Variable Orderings (Abstract)

William Adams , University of Texas, Austin
Masahiro Fujita , Fujitsu Labs of America, Sunnyvale, CA
Jawahar Jain , Fujitsu Labs of America, Sunnyvale, CA
pp. 631-638

The Design of a Cache-Friendly BDD Library (Abstract)

David E. Long , Lucent Technologies
pp. 639-645

Design of Experiments in BDD Variable Ordering: Lessons Learned (Abstract)

Justin E. Harlow , Duke University, Durham, NC
Franc Brglez , NC State U., Raleigh
pp. 646-652
Session 11C: System Synthesis Under Design Constraints

On-Line Scheduling of Hard Real-Time Tasks on Variable Voltage Processor (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Mani B. Srivastava , University of California, Los Angeles
Inki Hong , University of California, Los Angeles
pp. 653-656

Transforming Control-flow Intensive Designs to Facilitate Power Management (Abstract)

Anand Raghunathan , CCRL, NEC-USA, Princeton, NJ
Ganesh Lakshminarayana , Princeton University, NJ
Sujit Dey , University of California, San Diego
Niraj K. Jha , Princeton University, NJ
pp. 657-664

Synthesis of Application Specific Instructions for Embedded DSP Software (Abstract)

In-Cheol Park , Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
Hoon Choi , Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
Seung Ho Hwang , Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
Chong-Min Kyung , Korea Advanced Institute of Sciencea and Technology, Taejon, Korea
pp. 665-671
Session 11D: Functional Representation

Word-Level Decision Diagrams, WLCDs and Division (Abstract)

Thomas M. Weis , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
Christoph Scholl , Albert-Ludwigs-University, Germany
pp. 672-677

Polynomial Methods for Component Matching and Verification (Abstract)

James Smith , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
pp. 678-685

Symbolic Model Checking of Process Networks Using Interval Diagram Techniques (Abstract)

Lothar Thiele , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
Karsten Strehl , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 686-692
Session 12A: Embedded Tutorial - Interface Synthesis: A Vertical Slice from Digital Logic to Software Components

Interface Synthesis: A Vertical Slice from Digital Logic to Software Components (Abstract)

Luciano Lavagno , Politecnico di Torino, Italia
Ross B. Ortega , University of Washington, Bothell
Gaetano Borriello , University of Washington, Seattle
pp. 693-695
Session 12B: Embedded Tutorial - Dynamic Power Management of Electronic Systems

Dynamic Power Management of Electronic Systems (Abstract)

Luca Benini , DEIS - Universit? di Bologna
Giovanni De Micheli , CSL - Stanford University
Alessandro Bogliolo , DEIS - Universit? di Bologna
pp. 696-702
121 ms
(Ver 3.1 (10032016))