The Community for Technology Leaders
Computer-Aided Design, International Conference on (1997)
San Jose, CA
Nov. 9, 1997 to Nov. 13, 1997
ISBN: 0-8186-8200-0
TABLE OF CONTENTS

Foreword (PDF)

pp. xv

Reviewers (PDF)

pp. xix

Keynote Address (PDF)

pp. xxvi
Session 1A: Decision Diagram Applications, Moderators: Shin-ichi Minato and Jawahar Jain

PHDD: An Efficient Graph Representation for Floating Point Circuit Verification (Abstract)

Randal E. Bryant , Carnegie Mellon University
Yirng-An Chen , Carnegie Mellon University
pp. 2

Functional Simulation using Binary Decision Diagrams (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Christoph Scholl , Albert-Ludwigs-University
pp. 8

Generalized matching from theory to application (Abstract)

G. De Micheli , Comput. Syst. Lab., Stanford Univ., CA, USA
P. Vuillod , Comput. Syst. Lab., Stanford Univ., CA, USA
L. Benini , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 13
Session 1B: Optimization and Synthesis for Reactive Systems, Moderators: Rolf Ernst and Charles Rosenthal

Decomposition of timed decision tables and its use in presynthesis optimizations (Abstract)

R.K. Gupta , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Jian Li , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 22

A predictive system shutdown method for energy saving of event-driven computation (Abstract)

A.C.-H. Wu , Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
Chi-Hong Hwang , Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
pp. 28

Micro-Preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI Systems (Abstract)

Ramesh Karri , University of Massachusetts
Miodrag Potkonjak , University of California, Los Angeles
Kyosun Kim , University of Massachusetts
pp. 33
Session 1C: Estimation of Power Bounds, Moderators: Farid N. Najm and Wen-Zen Shen

Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs (Abstract)

Tan-Li Chou , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Zhanping Chen , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 40

Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits (Abstract)

Janak H. Patel , University of Illinois
Elizabeth M. Rudnick , University of Illinois
Michael S. Hsiao , Rutgers University
pp. 45

COSMOS: A Continuous Optimization Approach for Maximum Power Estimation of CMOS Circuits (Abstract)

Chuan-Yu Wang , Electrical and Computer Engineering Purdue University, West Lafayette
Kaushik Roy , Electrical and Computer Engineering Purdue University, West Lafayette
pp. 52
Session 1D: Block Krylov Methods for Interconnect Modeling, Moderators: Peter Feldmann and Jacob K. White

PRIMA: passive reduced-order interconnect macromodeling algorithm (Abstract)

L.T. Pileggi , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. Odabasioglu , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Celik , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 58

Multipoint Pade approximation using a rational block Lanczos algorithm (Abstract)

Jing Li , IBM Corp., Austin, TX, USA
T.V. Nguyen , IBM Corp., Austin, TX, USA
pp. 72
Session 2A: Multi-Level Synthesis and Covering Problem, Moderators: Robert J. Francis and Olivier Courdert

The Disjunctive Decomposition of Logic Functions (Abstract)

Valeria Bertacco , Stanford University
Maurizio Damiani , Synopsys, Inc
pp. 78

Speeding Up Technology-Independent Timing Optimization by Network Partitioning (Abstract)

Rajeev Murgai , Fujitsu Labs of America, Inc.
Masahiro Fujita , Fujitsu Labs of America, Inc.
Rajat Aggarwal , Lattice Semiconductor Corporation, Milpitas, CA
pp. 83

Negative Thinking by Incremental Problem Solving: Application to Unate Covering (Abstract)

Robert K. Brayton , University of California at Berkeley, CA 94720.
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley, CA 94720.
Tiziano Villa , PARADES
Evguenii I. Goldberg , University of California at Berkeley, CA 94720.
Luca P. Carloni , University of California at Berkeley, CA 94720.
pp. 91
Session 2B: Code Generation and Processor Design, Moderators: P.A. Subrahmanyam and Rolf Ernst

Application-Driven Synthesis of Core-Based Systems (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
William Mangione-Smith , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
Chunho Lee , University of California, Los Angeles
pp. 104

Power optimization using divide-and-conquer techniques for minimization of the number of operations (Abstract)

R. Karri , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA.
M. Potonjak , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA.
I. Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA.
pp. 108
Session 2C: High-Level Power Prediction and Reduction, Moderators: Chandu Visweswariah and Wen-Zen Shen

High-Level Area and Power Estimation for VLSI Circuits (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
Mahadevamurty Nemani , University of Illinois at Urbana-Champaign
pp. 114

Achievable Bounds On Signal Transition Activity (Abstract)

Ibrahim N. Hajj , Coordinated Science Laboratory University of Illinois at Urbana Champaign
Sumant Ramprasad , Coordinated Science Laboratory University of Illinois at Urbana Champaign
Naresh R. Shanbhag , Coordinated Science Laboratory University of Illinois at Urbana Champaign
pp. 126
Session 2D: Noise Analysis and Modeling, Moderators: Lawrence T. Pileggi and Jue Hsien Chern

Circuit Noise Evaluation by Pad? Approximation Based Model-Reduction Techniques (Abstract)

Peter Feldmann , Bell Laboratories Lucent Technologies
Roland W. Freund , Bell Laboratories Lucent Technologies
pp. 132

Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks (Abstract)

P. C. Elmendorf , IBM Microelectronics, Fishkill, NY
V. Narayanan , IBM T. J. Watson Research Center
K. L. Shepard , IBM T. J. Watson Research Center
Gutuan Zheng , IBM Microelectronics, Fishkill, NY
pp. 139

Efficient coupled noise estimation for on-chip interconnects (Abstract)

A. Devgan , Res. Lab., IBM Corp., Austin, TX, USA
pp. 147
Session 3A: High Level Validation, Moderators: Christos Papachristou and Joachim Kunkel

Verifying Correct Pipeline Implementation for Microprocessors (Abstract)

Jeremy Levitt , Computer Systems Laboratory, Stanford University
Kunle Olukotun , Computer Systems Laboratory, Stanford University
pp. 162

A Quantitative Approach to Functional Debugging (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 170
Session 3B: Timing Analysis, Moderators: Chandu Visweswariah and Wen-Zen Shen

Approximate Timing Analysis of Combinational Circuits under the XBD0 Model (Abstract)

Wilsin Gosti , University of California, Berkeley
Yuji Kukimoto , University of California, Berkeley
Alexander Saldanha , Cadence Berkeley Laboratories
Robert K. Brayton , University of California, Berkeley
pp. 176

Timing Analysis Based on Primitive Path Delay Fault Identification (Abstract)

Andrzej J. Strojwas , Carnegie Mellon University
Mukund Sivaraman , Carnegie Mellon University
pp. 182

Approximate Algorithms for Time Separation of Events (Abstract)

David L. Dill , Stanford University
Supratik Chakraborty , Stanford University
pp. 190
Session 4A: Embedded Tutorial
Session 4B: Embedded Tutorial
Session 5A: Sequential Circuit Optimization, Moderators: Marios Papaefthymiou and Narendra V. Shenoy

Sequential Optimisation without State Space Exploration (Abstract)

Adnan Aziz , University of Texas at Austin
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
Shaz Qadeer , University of California at Berkeley
Vigyan Singhal , Cadence Berkeley Labs
Robert K Brayton , University of California at Berkeley
Amit Mehrotra , University of California at Berkeley
pp. 208

Minimum Area Retiming with Equivalent Initial States (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Naresh Maheshwari , Iowa State University, Ames IA
pp. 216

Decomposition and technology mapping of speed-independent circuits using Boolean relations (Abstract)

A. Yakovlev , Univ. Politecnica de Catalunya, Barcelona, Spain
L. Lavagno , Univ. Politecnica de Catalunya, Barcelona, Spain
E. Pastor , Univ. Politecnica de Catalunya, Barcelona, Spain
A. Kondratyev , Univ. Politecnica de Catalunya, Barcelona, Spain
M. Kishinevsky , Univ. Politecnica de Catalunya, Barcelona, Spain
J. Cortadella , Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 220
Session 5B: Advanced Scheduling Techniques, Moderators: Miodrag M. Potkonjak and David Ku

Scheduling and binding bounds for RT-level symbolic execution (Abstract)

F. Brewer , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
C. Monahan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 230

High-level Scheduling Model and Control Synthesis for a Broad Range of Design Applications (Abstract)

Chih-Tung Chen , Unified Design System Laboratory, Motorola, Inc.
Kayhan Kucukcakar , Unified Design System Laboratory, Motorola, Inc.
pp. 236
Session 5C: Clock Design and Optimization, Moderators: Masato Edahiro and Jason Cong

Optimal Wire and Transistor Sizing for Circuits with Non-tree Topology (Abstract)

Abbas El Gamal , Stanford University
Lieven Vandenberghe , University of California, Los Angeles
Stephen Boyd , Stanford University
pp. 252

Clock-Tree Routing Realizing a Clock-Schedule for Semi-Synchronous Circuits (Abstract)

Yoji Kajitani , Tokyo Institute of Technology
Atsushi Takahashi , Tokyo Institute of Technology
Kazunori Inoue , Hitachi ULSI Engineering
pp. 260

A Hierarchical Decomposition Methodology for Multistage Clock Circuit (Abstract)

Rob A. Rutenbar , Carnegie Mellon University
Lawrence T. Pileggi , Carnegie Mellon University
Gary Ellis , IBM Microelectronics
pp. 266
Session 5D: Circuit Simulation and Optimization, Moderators: Ibrahim M. Elfadel and Wim van Bokhoven

Circuit Optimization via Adjoint Lagrangians (Abstract)

Andrew R. Conn , IBM T. J. Watson Research Center
Ruud A. Haring , IBM T. J. Watson Research Center
Chandu Visweswariah , IBM T. J. Watson Research Center
Chai Wah Wu , IBM T. J. Watson Research Center
pp. 281

State transformation in event driven explicit simulation (Abstract)

A. Devgan , Res. Lab., IBM Corp., Austin, TX, USA
T.V. Nguyen , Res. Lab., IBM Corp., Austin, TX, USA
pp. 289
Session 6A: New Ideas in Encoding, Moderators: Ellen M. Sentovich and Pranav Ashar

A Fast and Robust Exact Algorithm for Face Embedding (Abstract)

Robert K. Brayton , University of California at Berkeley
Evguenii I. Goldberg , Academy of Sciences of Belarus, Minsk
Tiziano Villa , PARADES
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
pp. 296

An Output Encoding Problem and a Solution Technique (Abstract)

Edward J. McCluskey , Stanford University
Subhasish Mitra , Stanford University
LaNae J. Avra , Stanford University
pp. 304
Session 6B: Synthesis with Complex Components, Moderators: Forrest D. Brewer and Kunle Olukotun

Resource Sharing in Hierarchical Synthesis (Abstract)

Wolfgang Rosenstiel , Universitaet Tuebingen
Oliver Bringmann , Forschungszentrum Informatik
pp. 318

Generalized resource sharing (Abstract)

R.A. Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Raje , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 326

Exploiting Off-Chip Memory Access Modes in High-Level Synthesis (Abstract)

Preeti Ranjan Panda , University of California, Irvine
Alexandru Nicolau , University of California, Irvine
Nikil D. Dutt , University of California, Irvine
pp. 333
Session 6C: Partitioning Part I, Moderators: Naveed Sherwani or Chung-Kuan Cheng

Replication for Logic Bipartitioning (Abstract)

Majid Sarrafzadeh , Northwestern University
Scott Hauck , Northwestern University
Morgan Enos , Northwestern University
pp. 342

Adaptive Methods for Netlist Partitioning (Abstract)

Lixin Su , Univ. of California, Berkeley
Andrew Mayer , Univ. of California, Berkeley
Wray L. Buntine , Univ. of California, Berkeley
A. Richard Newton , Univ. of California, Berkeley
pp. 356
Session 6D: Analog Modeling and Testing, Moderators: Wim van Bokhoven and Georges Gielen

A Behavioral Signal Path Modeling Methodology for Qualitative Insight in and Efficient Sizing of CMOS Opamps (Abstract)

Francky Leyn , Katholieke Universiteit Leuven, ESAT-MICAS
Willy Sansen , Katholieke Universiteit Leuven, ESAT-MICAS
Georges Gielen , Katholieke Universiteit Leuven, ESAT-MICAS
Walter Daems , Katholieke Universiteit Leuven, ESAT-MICAS
pp. 374
Session 7A: Sequential Circuit Verification, Chair: Carl P. Pixley and Gianpiero Cabodi

Reachability Analysis Using Partitioned-ROBDDs (Abstract)

Jawahar Jain , Fujitsu Labs of America
Amit Narayan , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
A. L. Sangiovanni-Vincentelli , University of California, Berkeley
Adrian J. Isles , University of California, Berkeley
pp. 388

Record and play: a structural fixed point iteration for sequential circuit verification (Abstract)

W. Kunz , Inst. of Comput. Sci. III, Potsdam Univ., Germany
D. Stoffel , Inst. of Comput. Sci. III, Potsdam Univ., Germany
pp. 394

Forward Model Checking Techniques Oriented to Buggy Designs (Abstract)

Hiroaki Iwashita , Fujitsu Laboratories Ltd.
Tsuneo Nakata , Fujitsu Laboratories Ltd.
pp. 400
Session 7B: BIST, Moderators: Janusz Rajski, or Ronald D. Blanton

A test synthesis technique using redundant register transfers (Abstract)

M. Baklashov , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 414

Built-In Test Generation for Synchronous Sequential Circuits (Abstract)

Sudhakar M. Reddy , Electrical and Computer Engineering Department, University of Iowa
Irith Pomeranz , Electrical and Computer Engineering Department, University of Iowa
pp. 421
Session 7C: Partitioning Part II, Moderators: Charles J. Alpert and Atsushi Takahashi

Hierarchical partitioning for field-programmable systems (Abstract)

D. Lewis , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Vi Chi Chan , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 428

Hybrid Spectral/Iterative Partitioning (Abstract)

Pak K. Chan , University of California, Santa Cruz
Martine Schlag , University of California, Santa Cruz
Jason Y. Zien , IBM Almaden Research Center, San Jose
pp. 436
Session 7D: Efficient Techniques for Parasitics Extraction, Moderators: David D. Ling and Sani R. Nassif

IES/sup 3/: a fast integral equation solver for efficient 3-dimensional extraction (Abstract)

S. Kapur , Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
D.E. Long , Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
pp. 448

FastPep: A Fast Parasitic Extraction Program for Complex Three-Dimensional Geometries (Abstract)

Nuno Marques , INESC/Cadence European Labs.
Jacob White , Massachusetts Institute of Technology
Mattan Kamon , Massachusetts Institute of Technology
pp. 456
Session 8A: Embedded Tutorial

EDA and the network (Abstract)

pp. 470
Session 8B: Embedded Tutorial: Interconnect Design for Deep Submicron ICs
Session 9A: Power Estimation and Modeling, Moderators: Kaushik Roy and Chandu Visweswariah

Accurate Power Estimation for Large Sequential Circuits (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
Joseph N. Kozhaya , University of Illinois at Urbana-Champaign
pp. 488

Fast power estimation for deterministic input streams (Abstract)

M. Poncino , Comput. Syst. Lab., Stanford Univ., CA, USA
L. Benini , Comput. Syst. Lab., Stanford Univ., CA, USA
R. Scarsi , Comput. Syst. Lab., Stanford Univ., CA, USA
E. Macii , Comput. Syst. Lab., Stanford Univ., CA, USA
G. De Micheli , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 494

A Power Modeling and Characterization Method for Macrocells Using Structure Information (Abstract)

Jing-Yang Jou , National Chiao Tung Univ.
Wen-Zen Shen , National Chiao Tung Univ.
Jiing-Yuan Lin , National Chiao Tung Univ.
pp. 502
Session 9B: Partitioning for HW/SW Codesign, Moderators: Allen C.-H. Wu and Frank N. Vahid

Hardware/Software Partitioning for Multi-function Systems (Abstract)

P. A. Subrahmanyam , Bell Labs, Holmdel, NJ
Asawaree Kalavade , Bell Labs, Holmdel, NJ
pp. 516
Session 9C: Placement, Moderators: Dwight D. Hill and Malgorzata Marek-Sadowska

NRG: Global and Detailed Placement (Abstract)

Maogang Wang , Northwestern University
Majid Sarrafzadeh , Northwestern University
pp. 532

Simulated Quenching: a New Placement Method for Module Generation (Abstract)

Shinji Sato , CAD Laboratory Fujitsu Laboratories Ltd.
pp. 538

A Signature Based Approach to Regularity Extraction (Abstract)

Ravi Varadarajan , Cadence Design Systems (MS 2B1)
Srinivasa R. Arikati , University of Memphis
pp. 542
Session 9D: Fault Simulation and Diagnosis, Moderator: Robert Aitken and Kwang-Ting Cheng

GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/I/sub DDQ/ testing environment (Abstract)

Tzuhao Chen , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
I.N. Hajj , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 555

A Deductive Technique for Diagnosis of Bridging Faults (Abstract)

W. Kent Fuchs , Purdue University
Srikanth Venkataraman , University of Illinois
pp. 562
Session 10A: Logic Synthesis for Low Power, Moderators: Jordi Cortadella and Luciano Lavagno

Low Power Logic Synthesis for XOR Based Circuits (Abstract)

Unni Narayanan , University of Illinois at Urbana-Champaign
C. L. Liu , University of Illinois at Urbana-Champaign
pp. 570

An Exact Gate Decomposition Algorithm for Low-Power Technology Mapping (Abstract)

D.F. Wong , University of Texas at Austin
Hai Zhou , University of Texas at Austin
pp. 575

Trace Driven Logic Synthesis - Application to Power Minimization (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
Patrick C. McGeer , Cadence Berkeley Laboratories
Luca P. Carloni , University of California at Berkeley
Alexander Saldanha , Cadence Berkeley Laboratories
pp. 581
Session 10B: Analysis of Real Time Systems, Moderators: Wayne Wolf and Ahmed A. Jerraya

Performance analysis of a system of communicating processes (Abstract)

S. Dey , C&C Res. Labs., NEC USA Inc., Princeton, NJ, USA
S. Bommu , C&C Res. Labs., NEC USA Inc., Princeton, NJ, USA
pp. 590

Embedded Program Timing Analysis Based On Path Clustering and Architecture Classification (Abstract)

Rolf Ernst , Technische Universitaet Braunschweig
Wei Ye , Technische Universitaet Braunschweig
pp. 598

Real Time Analysis and Priority Scheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System (Abstract)

Giovanni de Micheli , Gates Computer Science Building Stanford University
Vincent John Mooney, III , Gates Computer Science Building Stanford University
pp. 605
Session 10C: Interconnect Optimization, Moderators: Wayne W.-M. Dai and John M. Cohn

A New Approach to Simultaneous Buffer Insertion and Wire Sizing (Abstract)

Chris C. N. Chu , University of Texas at Austin
D. F. Wong , University of Texas at Austin
pp. 614

Optimal Shape Function for a Bi-directional Wire under Elmore Delay Model (Abstract)

Youxin Gao , The University of Texas at Austin
D.F. Wong , The University of Texas at Austin
pp. 622

Global interconnect sizing and spacing with consideration of coupling capacitance (Abstract)

Lei He , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Cheng-Kok Koh , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Zhigang Pan , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 628
Session 10D: Implication and Test Generation Techniques, Moderators: Pranav Ashar and Jawahar Jain

Test Generation for Primitive Path Delay Faults in Combinational Circuits (Abstract)

Prem R. Menon , University of Massachusetts
Ramesh C. Tekumalla , University of Massachusetts
pp. 636

Fast Identification of Untestable Delay Faults Using Implications (Abstract)

Janak Patel , University of Illinois at Urbana-Champaign
Vishwani D. Agrawal , AT&T Bell Laboratories
Keerthi Heragu , University of Illinois at Urbana-Champaign
pp. 642

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists (Abstract)

P. Tafertshofer , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
M. Henftling , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
A. Ganz , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 648
Session 11A: Technology Driven Synthesis, Moderators: K.-C. Chen and Shih-Chieh Chang

Library-less synthesis for static CMOS combinational logic circuits (Abstract)

S. Gavrilov , Res. Inst., Acad. of Sci., Moscow, Russia
S. Pullela , Res. Inst., Acad. of Sci., Moscow, Russia
A. Glebov , Res. Inst., Acad. of Sci., Moscow, Russia
A. Dharchoudhury , Res. Inst., Acad. of Sci., Moscow, Russia
S.C. Moore , Res. Inst., Acad. of Sci., Moscow, Russia
D.T. Blaauw , Res. Inst., Acad. of Sci., Moscow, Russia
R. Panda , Res. Inst., Acad. of Sci., Moscow, Russia
G. Vijayan , Res. Inst., Acad. of Sci., Moscow, Russia
pp. 658

Logic Synthesis for Large Pass Transistor Networks (Abstract)

Premal Buch , University of California, Berkeley
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
Amit Narayan , University of California, Berkeley
A. Richard Newton , University of California, Berkeley
pp. 663

An Exact Solution to Simultaneous Technology Mapping and Linear Placement Problem (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Jinan Lou , University of Southern California, Los Angeles
Amir H. Salek , University of Southern California, Los Angeles
pp. 671
Session 11B: System Specification and Product Engineering, Moderators: Bernard Courtois and Jerry R. Burch

A Statistical Analysis Methodology and Its Application to High-Density DRAMs (Abstract)

Won-Seong Lee , CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Chang-Hoon Choi , CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Jeong-Taek Kong , CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Jei-Hwan Yoo , CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
Sang-Hoon Lee , CAE, Semiconductor R & D Center, Samsung Electronics Co., LTD.
pp. 678

Fast Field Solver Programs for Thermal and Electrostatic Analysis of Microsystem Elements (Abstract)

Vladimir Székely , Technical University of Budapest
Márta Rencz , Technical University of Budapest
pp. 684

Java as a Specification Language for Hardware-Software Systems (Abstract)

Kunle Olukotun , Stanford University
Rachid Helaihel , Stanford University
pp. 690
Session 11C: Performance-Driven Routing, Moderators: D.F. Wong and Rajeev Jayaraman

Post-Route Optimization for Improved Yield Using a Rubber-Band Wiring Model (Abstract)

Jeffrey Z. Su , University of California, Santa Cruz
Wayne W. Dai , University of California, Santa Cruz
pp. 700

Delay Bounded Buffered Tree Construction for Timing Driven Floorplanning (Abstract)

Maggie Kang , University of California at Santa Cruz, CA, 95064
David LaPotin , IBM Austin Research Lab
Tom Dillinger , Rockwell Semiconductor
Wayne W.-M. Dai , University of California at Santa Cruz, CA, 95064
pp. 707

Interconnect layout optimization under higher-order RLC model (Abstract)

Cheng-Kok Koh , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 713
Session 11D: Test Theory and Applications, Moderators: Fadi Maamari and Sandeep K. Gupta

Test and Diagnosis of Faulty Logic Blocks in FPGAs (Abstract)

Tsi-Ming Tsai , National Chung-Hsing University
Sying-Jyan Wang , National Chung-Hsing University
pp. 722

Partial Scan Delay Fault Testing of Asynchronous Circuits (Abstract)

Michael Kishinevsky , The University of Aizu
Alexander Taubin , The University of Aizu
Alex Kondratyev , The University of Aizu
Luciano Lavagno , Politecnico di Torino
Alexander Saldanha , Cadence Berkeley Laboratories
pp. 728

Maximum independent sets on transitive graphs and their applications in testing and CAD (Abstract)

D. Kagaris , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas , Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 736
Session 12A: Embedded Tutorial
Session 12B: Embedded Tutorial

Author Index (PDF)

pp. 767
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