Foreword (PDF)

Conference Committee (PDF)

Technical Program Committee (PDF)

Reviewers (PDF)

Tutorial 1: Timing Analysis and Optimization: From Devices to Systems (PDF)

Tutorial 2: Design Technology for Building Wireless Systems (PDF)

Tutorial 3: Modeling and Synthesis of Behavior, Control and Dataflow (PDF)

Tutorial 4: Critical Technologies and Methodologies for Systems-On-Chips (PDF)

Keynote Address (PDF)

PHDD: An Efficient Graph Representation for Floating Point Circuit Verification (Abstract)

Functional Simulation using Binary Decision Diagrams (Abstract)

Generalized matching from theory to application (Abstract)

Decomposition of timed decision tables and its use in presynthesis optimizations (Abstract)

A predictive system shutdown method for energy saving of event-driven computation (Abstract)

Micro-Preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI Systems (Abstract)

Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs (Abstract)

Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits (Abstract)

COSMOS: A Continuous Optimization Approach for Maximum Power Estimation of CMOS Circuits (Abstract)

PRIMA: passive reduced-order interconnect macromodeling algorithm (Abstract)

A Block Rational Arnoldi Algorithm for Multipoint Passive Model-Order Reduction of Multiport RLC Networks (Abstract)

Multipoint Pade approximation using a rational block Lanczos algorithm (Abstract)

The Disjunctive Decomposition of Logic Functions (Abstract)

Speeding Up Technology-Independent Timing Optimization by Network Partitioning (Abstract)

Negative Thinking by Incremental Problem Solving: Application to Unate Covering (Abstract)

DSP Address Optimization Using A Minimum Cost Circulation Technique (Abstract)

Application-Driven Synthesis of Core-Based Systems (Abstract)

Power optimization using divide-and-conquer techniques for minimization of the number of operations (Abstract)

High-Level Area and Power Estimation for VLSI Circuits (Abstract)

Optimizing Computations in a Transposed Direct Form Realization of Floating-Point LTI-FIR Systems (Abstract)

Achievable Bounds On Signal Transition Activity (Abstract)

Circuit Noise Evaluation by Pad? Approximation Based Model-Reduction Techniques (Abstract)

Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks (Abstract)

Efficient coupled noise estimation for on-chip interconnects (Abstract)

Efficient Circuit Partitioning to Extend Cycle Simulation Beyond Synchronous Circuits (Abstract)

Verifying Correct Pipeline Implementation for Microprocessors (Abstract)

A Quantitative Approach to Functional Debugging (Abstract)

Approximate Timing Analysis of Combinational Circuits under the XBD0 Model (Abstract)

Timing Analysis Based on Primitive Path Delay Fault Identification (Abstract)

Approximate Algorithms for Time Separation of Events (Abstract)

4A.1: Microelectromechanical Systems (PDF)

Optimization Techniques for High-Performance Digital Circuits (Abstract)

Sequential Optimisation without State Space Exploration (Abstract)

Minimum Area Retiming with Equivalent Initial States (Abstract)

Decomposition and technology mapping of speed-independent circuits using Boolean relations (Abstract)

Scheduling and binding bounds for RT-level symbolic execution (Abstract)

High-level Scheduling Model and Control Synthesis for a Broad Range of Design Applications (Abstract)

Wavesched: A Novel Scheduling Technique for Control-flow Intensive Behavioral Descriptions (Abstract)

Optimal Wire and Transistor Sizing for Circuits with Non-tree Topology (Abstract)

Clock-Tree Routing Realizing a Clock-Schedule for Semi-Synchronous Circuits (Abstract)

A Hierarchical Decomposition Methodology for Multistage Clock Circuit (Abstract)

A New High-Order Absolutely-Stable Explicit Numerical Integration Algorithm for the Time-Domain Simulation of Nonlinear Circuits (Abstract)

Circuit Optimization via Adjoint Lagrangians (Abstract)

State transformation in event driven explicit simulation (Abstract)

A Fast and Robust Exact Algorithm for Face Embedding (Abstract)

An Output Encoding Problem and a Solution Technique (Abstract)

OPTIMIST: State Minimization for Optimal 2-Level Logic Implementation (Abstract)

Resource Sharing in Hierarchical Synthesis (Abstract)

Generalized resource sharing (Abstract)

Exploiting Off-Chip Memory Access Modes in High-Level Synthesis (Abstract)

Replication for Logic Bipartitioning (Abstract)

Partitioning Around Roadblocks: Tackling Constraints with Intermediate Relaxations (Abstract)

Adaptive Methods for Netlist Partitioning (Abstract)

Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams (Abstract)

A Behavioral Signal Path Modeling Methodology for Qualitative Insight in and Efficient Sizing of CMOS Opamps (Abstract)

Test Generation for Comprehensive Testing of Linear Analog Circuits Using Transient response Sampling (Abstract)

Reachability Analysis Using Partitioned-ROBDDs (Abstract)

Record and play: a structural fixed point iteration for sequential circuit verification (Abstract)

Forward Model Checking Techniques Oriented to Buggy Designs (Abstract)

BIST TPG for faults in system backplanes (Abstract)

A test synthesis technique using redundant register transfers (Abstract)

Built-In Test Generation for Synchronous Sequential Circuits (Abstract)

Hierarchical partitioning for field-programmable systems (Abstract)

Hybrid Spectral/Iterative Partitioning (Abstract)

Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering (Abstract)

IES/sup 3/: a fast integral equation solver for efficient 3-dimensional extraction (Abstract)

FastPep: A Fast Parasitic Extraction Program for Complex Three-Dimensional Geometries (Abstract)

Transform Domain Techniques for Efficient Extraction of Substrate Parasitics (Abstract)

EDA and the network (Abstract)

Interconnect Layout Optimization Under Higher-Order RLC Model (Abstract)

Accurate Power Estimation for Large Sequential Circuits (Abstract)

Fast power estimation for deterministic input streams (Abstract)

A Power Modeling and Characterization Method for Macrocells Using Structure Information (Abstract)

Transformational Partitioning for Co-Design of Multiprocessor Systems (Abstract)

Hardware/Software Partitioning for Multi-function Systems (Abstract)

MOGAC: A Multiobjective Genetic Algorithm for the Co-Synthesis of Hardware-Software Embedded Systems (Abstract)

NRG: Global and Detailed Placement (Abstract)

Simulated Quenching: a New Placement Method for Module Generation (Abstract)

A Signature Based Approach to Regularity Extraction (Abstract)

Fault Simulation of Interconnect Opens in Digital CMOS Circuits (Abstract)

GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/I/sub DDQ/ testing environment (Abstract)

A Deductive Technique for Diagnosis of Bridging Faults (Abstract)

Low Power Logic Synthesis for XOR Based Circuits (Abstract)

An Exact Gate Decomposition Algorithm for Low-Power Technology Mapping (Abstract)

Trace Driven Logic Synthesis - Application to Power Minimization (Abstract)

Performance analysis of a system of communicating processes (Abstract)

Embedded Program Timing Analysis Based On Path Clustering and Architecture Classification (Abstract)

Real Time Analysis and Priority Scheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System (Abstract)

A New Approach to Simultaneous Buffer Insertion and Wire Sizing (Abstract)

Optimal Shape Function for a Bi-directional Wire under Elmore Delay Model (Abstract)

Global interconnect sizing and spacing with consideration of coupling capacitance (Abstract)

Test Generation for Primitive Path Delay Faults in Combinational Circuits (Abstract)

Fast Identification of Untestable Delay Faults Using Implications (Abstract)

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists (Abstract)

Library-less synthesis for static CMOS combinational logic circuits (Abstract)

Logic Synthesis for Large Pass Transistor Networks (Abstract)

An Exact Solution to Simultaneous Technology Mapping and Linear Placement Problem (Abstract)

A Statistical Analysis Methodology and Its Application to High-Density DRAMs (Abstract)

Fast Field Solver Programs for Thermal and Electrostatic Analysis of Microsystem Elements (Abstract)

Java as a Specification Language for Hardware-Software Systems (Abstract)

Post-Route Optimization for Improved Yield Using a Rubber-Band Wiring Model (Abstract)

Delay Bounded Buffered Tree Construction for Timing Driven Floorplanning (Abstract)

Interconnect layout optimization under higher-order RLC model (Abstract)

Test and Diagnosis of Faulty Logic Blocks in FPGAs (Abstract)

Partial Scan Delay Fault Testing of Asynchronous Circuits (Abstract)

Maximum independent sets on transitive graphs and their applications in testing and CAD (Abstract)

Verifying Hardware in its Software Context (Abstract)

Simulation methods for RF integrated circuits (Abstract)

Author Index (PDF)