The Community for Technology Leaders
Computer-Aided Design, International Conference on (1996)
San Jose, CA
Nov. 10, 1996 to Nov. 14, 1996
ISSN: 1092-3152
ISBN: 0-8186-7597-7
TABLE OF CONTENTS
Session 1A: Technology Mapping, Moderators: Sujit Dey, Bob Francis

Logic optimization by output phase assignment in dynamic logic synthesis (Abstract)

A. Bjorksten , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
T.E. Rosser , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Puri , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 2

A New Method Towards Achieving Global Optimality in Technology Mapping (Abstract)

Kewal K. Saluja , University of Wisconsin-Madison
Wen Xiaoqing , Akita University
pp. 9

An Iterative Area/Performance Trade-Off Algorithm for LUT-Based FPGA Technology Mapping (Abstract)

Jing-Yang Jou , National Chiao Tung University
Wen-Zen Shen , National Chiao Tung University
Juinn-Dar Huang , National Chiao Tung University
pp. 13
Session 1B: Interconnect Characterization and Analysis, Moderators: John Cohn, Chandu Visweswariah

An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data (Abstract)

R. Achar , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Guowu Zheng , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M. Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Qi-Jun Zhang , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 20

Automatic netlist extraction for measurement-based characterization of off-chip interconnect (Abstract)

S.D. Corey , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
A.T. Yang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 24

Analytical delay models for VLSI interconnects under ramp input (Abstract)

A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
K. Masuko , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S. Muddu , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 30
Session 1C: High Performance Routing Synthesis, Moderators: Chung Kuan Cheng, Ren-Song Tsay

Optimal non-uniform wire-sizing under the Elmore delay model (Abstract)

Hai Zhou , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Chung-Ping Chen , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 38

Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization (Abstract)

Jason Cong , University of California, Los Angeles
Takumi Okamoto , NEC Corporation
pp. 44

Clock Tree Synthesis For Multi-Chip Modules (Abstract)

Sachin S. Sapatnekar , Iowa State University
Daksh Lehther , Iowa State University
pp. 50
Session 1D: Sequential Circuit Testing, Moderators: Janusz Rajski or Sandeep Gupta

Sequential redundancy identification using recursive learning (Abstract)

D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Wanlin Cao , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 56

Identification of unsettable flip-flops for partial scan and faster ATPG (Abstract)

I. Hartanto , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
V. Boppana , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 63

Simulation-Based Techniques for Dynamic Test Sequence Compaction (Abstract)

Elizabeth M. Rudnick , University of Illinois
Janak H. Patel , University of Illinois
pp. 67
Session 2A: Formal Verification I, Moderators: Jerry Burch, Felice Balarin

Tearing based automatic abstraction for CTL model checking (Abstract)

F. Somenzi , ECEN Campus, Colorado Univ., Boulder, CO, USA
Woohyuk Lee , ECEN Campus, Colorado Univ., Boulder, CO, USA
Jae-Young Jang , ECEN Campus, Colorado Univ., Boulder, CO, USA
G. Hachtel , ECEN Campus, Colorado Univ., Boulder, CO, USA
A. Pardo , ECEN Campus, Colorado Univ., Boulder, CO, USA
pp. 76

CTL Model Checking Based on Forward State Traversal (Abstract)

Tsuneo Nakata , Fujitsu Laboratories Ltd.
Hiroaki Iwashita , Fujitsu Laboratories Ltd.
Fumiyasu Hirose , Fujitsu Laboratories Ltd.
pp. 82

VERILAT: verification using logic augmentation and transformations (Abstract)

M. Chatterjee , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D. Paul , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 88
Session 2B: System Design: Synthesis and Compilation, Moderators: Rajesh K. Gupta, Hiroto Yasuura

Software Synthesis through Task Decomposition by Dependency Analysis (Abstract)

Kiyoung Choi , Seoul National University
Youngsoo Shin , Seoul National University
pp. 98

Synthesis of reusable DSP cores based on multiple behaviors (Abstract)

C.A. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Wei Zhao , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 103

Algorithms for Address Assignment in DSP Code Generation (Abstract)

Rainer Leupers , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 109
Session 2C: Timing Analysis, Moderators: Marios Papaefthymiou, Thomas G. Szymanski

An Approximate Timing Analysis Method for Datapath Circuits (Abstract)

John P. Hayes , The University of Michigan
Karem A. Sakallah , The University of Michigan
Hakan Yalcin , The University of Michigan
pp. 114

Static Timing Analysis for Self Resetting Circuits (Abstract)

Bruce M. Fleischer , IBM T.J Watson Research Center
Barbara A. Chappell , Intel Corporation
Vinod Narayanan , IBM T.J Watson Research Center
pp. 119

Timing verification of sequential domino circuits (Abstract)

K.A. Sakallah , EECS Dept., Michigan Univ., Ann Arbor, MI, USA
T. Mudge , EECS Dept., Michigan Univ., Ann Arbor, MI, USA
D. Van Campenhout , EECS Dept., Michigan Univ., Ann Arbor, MI, USA
pp. 127
Session 2D: Support for High Level Design, Moderator: Michaela Guiney

Basic Concepts for an HDL Reverse Engineering Tool-Set (Abstract)

Bernhard Wunder , University of Karlsruhe
Gunther Lehmann , University of Karlsruhe
Klaus D. Mueller-Glaser , University of Karlsruhe
pp. 134

Sensitivity Analysis of Iterative Design Processes (Abstract)

Rik Vigeland , Mentor Graphics Corporation
Jay B. Brockman , University of Notre Dame
Eric W. Johnson , University of Notre Dame
pp. 142
Session 3A: Power and Performance in High Level Synthesis, Moderators: Forrest Brewer, Wolfgang Rosenstiel

Register-transfer level estimation techniques for switching activity and power consumption (Abstract)

N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Raghunathan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Dey , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 158
Session 3B: High-Performance Circuit Optimization, Moderators: Willem van Bokhoven, Georges Gielen

Optimization of Custom MOS Circuits by Transistor Sizing (Abstract)

Gregory L. Morrill , IBM Microelectronics Division
Andrew R. Conn , IBM T. J. Watson Research Center
Paula K. Coulman , IBM Microelectronics Division
Chandu Visweswariah , IBM T. J. Watson Research Center
Ruud A. Haring , IBM T. J. Watson Research Center
pp. 174

An efficient approach to simultaneous transistor and interconnect sizing (Abstract)

Lei He , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Jason Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 181

Generalized Constraint Generation in the Presence of Non-Deterministic Parasitics (Abstract)

Edoardo Charbon , Cadence Design Systems Inc.
Paolo Miliozzi , University of California, Berkeley
Enrico Malavasi , Cadence Design Systems Inc.
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
pp. 187
Session 3C: Circuit Partitioning, Moderators: Jason Kong, Rajeev Jayaraman

VLSI circuit partitioning by cluster-removal using iterative improvement techniques (Abstract)

Wenyong Deng , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Shantanu Dutt , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 194

Multi-level Spectral Hypergraph Partitioning with Arbitrary Vertex Sizes (Abstract)

Pak K. Chan , University of California at Santa Cruz
Jason Y. Zien , University of California at Santa Cruz
Martine D. F. Schlag , University of California at Santa Cruz
pp. 201

Minimum Replication Min-Cut Partitioning (Abstract)

D. F. Wong , University of Texas at Austin
Wai-Kei Mak , University of Texas at Austin
pp. 205
Session 3D: ATPG, Moderators: Wolfgang Kunz, Dhiraj K. Pradhan

Compact and Complete Test Set Generation for Multiple Stuck-Faults (Abstract)

Alok Agrawal , University of California Berkeley
Luciano Lavagno , Cadence Berkeley Laboratories
Alexander Saldanha , Cadence Berkeley Laboratories
Alberto L. Sangiovanni-Vincentelli , University of California Berkeley
pp. 212
Session 4A: Embedded Tutorial, Presenter: Edward A. Lee

Comparing models of computation (Abstract)

A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.A. Lee , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 234
Session 4B: Embedded Tutorial, Presenters: Nick P. van der Meijs, Theo Smedes
Session 5A: Implication-Based Logic Synthesis, Moderators: Michel Berkelaar, Albert Wang

A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications (Abstract)

Hiroshi Sawada , NTT Communication Science Laboratories
Akira Nagoya , NTT Communication Science Laboratories
Shigeru Yamashita , NTT Communication Science Laboratories
pp. 254

Fast Boolean optimization by rewiring (Abstract)

Shih-Chieh Chang , Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
L.P.P.P. van Ginneken , Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
M. Marek-Sadowska , Nat. Chung-Cheng Univ., Jay-Yi, Taiwan
pp. 262
Session 5B: Advanced Numerical Simulation Techniques, Moderators: Chandu Visweswariah, Willem van Bokhoven

A Coordinate-Transformed Arnoldi Algorithm for Generating Guaranteed Stable Reduced-Order Models of RLC Circuits (Abstract)

Jacob White , Massachusetts Institute of Technology
Mattan Kamon , Massachusetts Institute of Technology
Ibrahim Elfadel , IBM T. J. Watson Research Center
L. Miguel Silveira , IST/INESC
pp. 288
Session 5C: Robust RoutingGary Yaep, Takashi Kambe

Post Global Routing Crosstalk Risk Estimation and Reduction (Abstract)

Ernest S. Kuh. , Univ. of CA at Berkeley
Dongsheng Wang , Univ. of CA at Berkeley
Tianxiong Xue , Univ. of CA at Berkeley
pp. 302

An Optimal Algorithm for River Routing with Crosstalk Constraints (Abstract)

Hai Zhou , University of Texas at Austin
D. F. Wong , University of Texas at Austin
pp. 310

Jitter-tolerant clock routing in two-phase synchronous systems (Abstract)

W.W.-M. Dai , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
J.G. Xi , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 316
Session 5D: BIST and DFT, Moderators: Yervant Zorian, Robert C. Aitken

Enhancing High-Level Control-Flow for Improved Testability (Abstract)

Frank F. Hsu , University of Illinois
Janak H. Patel , University of Illinois
Elizabeth M. Rudnick , University of Illinois
pp. 322

A Design for Testability Technique for RTL Circuits Using Control/Data Flow Extraction (Abstract)

Anand Raghunathan , Princeton University
Indradeep Ghosh , Princeton University
Niraj K. Jha , Princeton University
pp. 329

Bit-Flipping BIST (Abstract)

Gundolf Kiefer , University of Stuttgart, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Germany
pp. 337
Session 6A: Formal Verification II, Moderators: Fabio Somenzi, Ellen M. Sentovich

Improved Reachability Analysis of Large Finite State Machines (Abstract)

Gianpiero Cabodi , Politecnico di Torino
Stefano Quer , Politecnico di Torino
Paolo Camurati , Politecnico di Torino
pp. 354

ACV: An Arithmetic Circuit Verifier (Abstract)

Yirng-An Chen , Carnegie Mellon University
Randal E. Bryant , Carnegie Mellon University
pp. 361
Session 6B: Yield and Technology Modeling, Moderators: Jacob K. White, David Ling

Hierarchical Statistical Characterization of Mixed-Signal Circuits Using Behavioral Modeling (Abstract)

Carlo Guardiani , SGS-Thomson Microelectronics
Stefano Zanella , Universita degli Studi di Padova
Eric Felt , University of California, Berkeley
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
pp. 374

A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects (Abstract)

W. Hong , Dept. of Radio Eng., Southeast Univ., Nanjing, China
B. Song , Dept. of Radio Eng., Southeast Univ., Nanjing, China
H. Ji , Dept. of Radio Eng., Southeast Univ., Nanjing, China
Z. Zhu , Dept. of Radio Eng., Southeast Univ., Nanjing, China
W. Sun , Dept. of Radio Eng., Southeast Univ., Nanjing, China
W. Wei-Ming Dai , Dept. of Radio Eng., Southeast Univ., Nanjing, China
pp. 381
Session 6C: Topics in Power and Timing Analysis, Moderators: Thomas G. Szymanski, Murray Hill

Inaccuracies in Power Estimation During Logic Synthesis (Abstract)

Chandu Visweswariah , IBM T.J. Watson Research Center
Daniel Brand , IBM T.J. Watson Research Center
pp. 388

Clock Skew Optimization for Ground Bounce Control (Abstract)

Forrest Brewer , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Hien Ha , University of California, Santa Barbara
Ashok Vittal , Silicon Graphics Inc.
pp. 395

A Power Modeling and Characterization Method for the CMOS Standard Cell Library (Abstract)

Wen-Zen Shen , National Chiao Tung Univ.
Jing-Yang Jou , National Chiao Tung Univ.
Jiing-Yuan Lin , National Chiao Tung Univ.
pp. 400
Session 6D: Verification and Fault Tolerance, Moderators: Kunle Olukotun, Steve Tjiang

Unit Delay Simulation with the Inversion Algorithm (Abstract)

William J. Schilp , University of South Florida
Peter M. Maurer , University of South Florida
pp. 412
Session 7A: Extending the Scope of High-Level Synthesis, Moderators: Don MacMillen, Yuon-Long Lin

Latch Optimization in Circuits Generated from High-level Descriptions (Abstract)

Horia Toma , Ecole Nationale Superieure des Mines de Paris
Ellen M. Sentovich , Ecole Nationale Superieure des Mines de Paris
Gerard Berry , Ecole Nationale Superieure des Mines de Paris
pp. 428

An Algorithm for Synthesis of System-Level Interface Circuits (Abstract)

Rajesh K. Gupta , University of Illinois at Urbana-Champaign
Ki-Seok Chung , University of Illinois at Urbana-Champaign
C.L. Liu , University of Illinois at Urbana-Champaign
pp. 442
Session 7B: Analog CAD and Methodology, Moderators: Georges Gielen, John Cohn

An Algorithm for Power Estimation in Switched-Capacitor Circuits (Abstract)

Giorgio Casinovi , Georgia Tech Research Institute
Chad Young , Georgia Institute of Technology
Paul Kerstetter , Georgia Institute of Technology
Jonathan Fowler , Georgia Institute of Technology
pp. 450

Semi-Analytical Techniques for Substrate Characterization in the Design of Mixed-Signal ICs (Abstract)

Ranjit Gharpurey , Texas Instruments Inc.
Robert G. Meyer , University of California, Berkeley, CA
Edoardo Charbon , Cadence Design Systems Inc.
Alberto Sangiovanni-Vincentelli , University of California, Berkeley, CA
pp. 455

A Video Driver System Designed Using a Top-Down, Constraint-Driven Methodology (Abstract)

Alper Demir , University of California, Berkeley
Alberto Sangiovanni-Vincentelli , University of California, Berkeley
Paolo Miliozzi , University of California, Berkeley
Henry Chang , Cadence Design Systems, Inc.
Iasson Vassiliou , University of California, Berkeley
Edoardo Charbon , Cadence Design Systems, Inc.
pp. 463
Session 7C: Partitioning and Floorplan, Moderators: Martin D.F. Wong, Frank M. Johannes

Hierarchical Partitioning (Abstract)

Klaus Harbich , University of Hanover
Erich Barke , University of Hanover
Dirk Behrens , University of Hanover
pp. 470

Module Placement on BSG-Structure and IC Layout Applications (Abstract)

Kunihiro Fugiyoshi , Japan Advanced Institute of Science and Technology (JAIST)
Yoji Kajitani , Tokyo Institute of Technology
Shigetoshi Nakatake , Tokyo Institute of Technology
Hiroshi Murata , Japan Advanced Institute of Science and Technology (JAIST)
pp. 484
Session 7D: Delay Fault Test, Moderators: E.J. McCluskey, Ray Mercer

SIGMA: A Simulator for Segment Delay Faults (Abstract)

Keerthi Heragu , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 502
Session 8A: Embedded Tutorial, Presenter: Gordon W. Roberts

Metrics, techniques and recent developments in mixed-signal testing (Abstract)

G.W. Roberts , Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
pp. 514
Session 8B: Embedded Tutorial, Presenters: Ken L. Shepard, Vinod Narayanan

Noise in Deep Submicron Digital Design (Abstract)

Vinod Narayanan , IBM T. J. Watson Research Center
Kenneth L. Shepard , IBM T. J. Watson Research Center
pp. 524
Session 9A: Panel
Session 10A: BDD Applications and Techniques, Moderators: Albert Wang, Sujit Dey

Efficient Solution of Systems of Boolean Equations (Abstract)

Giorgio Casinovi , Georgia Tech Research Institute
Scott Woods , Georgia Institute of Technology
pp. 542

Partitioned ROBDDs-a compact, canonical and efficiently manipulable representation for Boolean functions (Abstract)

A. Narayan , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J. Jain , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M. Fujita , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 547
Session 10B: Advances in Transmission Line Analysis, Moderators: Chandu Visweswariah, Rob A. Rutenbar

Simulation and Sensitivity Analysis of Transmission Line Circuits by the Characteristics Method (Abstract)

Ernest S. Kuh , University of California at Berkeley
Janet Meiling Wang , University of California at Berkeley
Jun-Fa Mao , University of California at Berkeley
pp. 556

Efficient Time-Domain Simulation of Frequency-Dependent Elements (Abstract)

Sharad Kapur , Lucent Technologies
Jaijeet Roychowdhury , Lucent Technologies
David E. Long , Lucent Technologies
pp. 569
Session 1OC: Power and Current Modeling, Moderators: Farid N. Najm, Jyuo-Min Shyu

Statistical sampling and regression analysis for RT-Level power evaluation (Abstract)

M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Cheng-Ta Hsieh , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Chih-Shun Ding , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Qing Wu , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 583

Expected Current Distributions for CMOS Circuits (Abstract)

Ronald A. Rohrer , Carnegie Mellon University
Dennis J. Ciplickas , PDF Solutions, Inc.
pp. 589
Session 10D: Mixed-Signal Testing, Moderators: Ranga Vemuri, Gordon Roberts

Metrology for analog module testing using analog testability bus (Abstract)

Yue-Tsang Chen , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Jye Jou , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Yuan-Tzu Ting , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Chanchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 594

ABILBO: Analog BuILt-in Block Observer (Abstract)

Salvador Mir , TIMA Laboratory
Leandro Pulz , DELET/UFRGS
Marcelo Lubaszewski , DELET/UFRGS
pp. 600

Design of Robust Test Criteria in Analog Testing (Abstract)

Walter M. Lindermeir , Institute of Electronic Design Automation
pp. 604
Session 11A: Logic Synthesis, Moderators: Narendra Shenoy, Carl Pixley

Metamorphosis: State Assignment by Retiming and Re-encoding (Abstract)

Balakrishnan Iyer , University of Massachusetts at Amherst
Maciej Ciesielski , University of Massachusetts at Amherst
pp. 614

The Case for Retiming with Explicit Reset Circuitry (Abstract)

Robert K. Brayton , University of California at Berkeley
Sharad Malik , Princeton University
Vigyan Singhal , Cadence Berkeley Labs
pp. 618
Session 11B: System Level Optimization and Validation, Moderators: P.A. Subrahmanyam, Masaharu Imai

Power optimization in disk-based real-time application specific systems (Abstract)

I. Hong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
M. Potkonjak , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 634

Generation of BDDs from Hardware Algorithm Descriptions (Abstract)

Shin-ichi Minato , NTT System Electronics Laboratories
pp. 644
Session 11C: Special Topics In Physical Design, Moderators: Dwight Hill, Atushi Takahashi

Directional Bias and Non-Uniformity in FPGA Global Routing Architectures (Abstract)

Vaughn Betz , University of Toronto
Jonathan Rose , University of Toronto
pp. 652

Width Minimization of Two-Dimensional CMOS Cells Using Integer Programming (Abstract)

John P. Hayes , The University of Michigan
Avaneendra Gupta , The University of Michigan
pp. 660

Interchangeable pin routing with application to package layout (Abstract)

W.W.-M. Dai , Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
J. Darnauer , Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
Man-Fai Yu , Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 668
Session 11D: Fault Diagnosis, Moderators: Rabindra K. Roy, Justin Harlow

A Coloring Approach to the Structural Diagnosis of Interconnects (Abstract)

X. T. Chen , Texas A&M University
F. Lombardi , Texas A&M University
pp. 676

Integrated fault diagnosis targeting reduced simulation (Abstract)

V. Boppana , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 681

An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards (Abstract)

K. Chakraborty , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 685
Session 12A: Embedded Tutorial, Presenters: W. Maly, H. Heineken, J. Khare, P.K. Nag

Design for manufacturability in submicron domain (Abstract)

H. Heineken , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J. Khare , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P.K. Nag , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 690
Session 12B: Embedded Tutorial, Presenter: L.P.P.P. van Ginneken, N.V. Shenoy, R.H.J.M. Otten

Author Index (PDF)

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