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Computer-Aided Design, International Conference on (1996)
San Jose, CA
Nov. 10, 1996 to Nov. 14, 1996
ISSN: 1092-3152
ISBN: 0-8186-7597-7
pp: 63
I. Hartanto , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
V. Boppana , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
ABSTRACT
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.
INDEX TERMS
logic testing; unsettable flip-flops identification; partial scan; ATPG; state justification; sequential circuits test generation; state elements; hip-hops; transformed circuits; deterministic test generation; difficult-to-set hip-hops; ISCAS89 circuits
CITATION
I. Hartanto, W.K. Fuchs, V. Boppana, "Identification of unsettable flip-flops for partial scan and faster ATPG", Computer-Aided Design, International Conference on, vol. 00, no. , pp. 63, 1996, doi:10.1109/ICCAD.1996.568941
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