The Community for Technology Leaders
Computer-Aided Design, International Conference on (1995)
San Jose, CA
Nov. 5, 1995 to Nov. 9, 1995
ISBN: 0-8186-7213-7
TABLE OF CONTENTS

Foreword (PDF)

pp. xv

Reviewers (PDF)

pp. xx
Session 1A: Formal Verification, Moderators: Ellen M. Sentovich, Sophia Antipolis, David E. Long

Efficient Validity Checking for Processor Verification (Abstract)

Robert B. Jones , Computer Systems Laboratory
David L. Dill , Computer Systems Laboratory
Jerry R. Burch , Cadence Berkeley Laboratories
pp. 0002

The Formal Verification of a Pipelined Double-Precision IEEE Floating-Point Multiplier (Abstract)

Mark D. Aagaard , University of British Columbia
Carl-Johan H. Seger , University of British Columbia
pp. 0007

Extracting RTL Models from Transistor Netlists (Abstract)

Kanwar Jit Singh , AT&T Bell Laboratories
P.A. Subrahmanyam , AT&T Bell Laboratories
pp. 0011
Session 1B: Power Analysis, Moderators: Farid N. Najm, Sharad Malik

Switching Activity Analysis using Boolean Approximation Method (Abstract)

Taku Uchino , Toshiba Corporation
Fumihiro Minami , Toshiba Corporation
Takashi Mitsuhashi , Toshiba Corporation
Nobuyuki Goto , Toshiba Corporation
pp. 0020

Estimation and Bounding of Energy Consumption in Burst-Mode Control Circuits (Abstract)

Peter A. Beerel , University of Southern California
Pei-Chuan Yeh , University of Southern California
Kenneth Y. Yun , University of California, San Diego
Steven M. Nowick , Columbia University
pp. 0026

Statistical estimation of sequential circuit activity (Abstract)

T.-L. Chou , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 0034
Session 1C: Interconnect Modeling, Moderators: David Ling, Keith Nabors

Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect (Abstract)

M. Chou , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 0040

Addressing high frequency effects in VLSI interconnects with full wave model and CFH (Abstract)

R. Achar , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M.S. Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Q.J. Zhang , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 0053
Session 1D: Issues in Clock Design, Moderators: M. Marek-Sadowska, Ren-Song Tsay

Activity-Driven Clock Design for Low Power Circuits (Abstract)

Gustavo E. Tellez , Northwestern University
Amir Farrahi , Northwestern University
Majid Sarrafzadeh , Northwestern University
pp. 0062

Bounded-Skew Clock and Steiner Routing Under Elmore Delay (Abstract)

Jason Cong , UCLA Dept. of Computer Science
Andrew B. Kahng , UCLA Dept. of Computer Science
Cheng-Kok Koh , UCLA Dept. of Computer Science
C.-W. Albert Tsao , UCLA Dept. of Computer Science
pp. 0066
Session 2A: DCs and DDs in Logic Synthesis, Moderators: Michel Berkelaar, Sujit Dey

Who are the Variables in Your Neighborhood (Abstract)

Shipra Panda , University of Colorado
Fabio Somenzi , University of Colorado
pp. 0074

Efficient Construction of Binary Moment Diagrams for Verifying Arithmetic Circuits (Abstract)

Kiyoharu Hamaguchi , Kyoto University
Shuzo Yajima , Kyoto University
Akihito Morita , Tokio Marine & Fire Insurance Co.
pp. 0078

Be careful with don't cares (Abstract)

D. Brand , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.A. Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Stok , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 0083
Session 2B: Advances in BIST, Moderators: Yervant Zorian, Sandeep Gupta

Pattern Generation for a Deterministic BIST Scheme (Abstract)

Sybille Hellebrand , University of Siegen, Germany
Birgit Reeb , University of Siegen, Germany
Hans-Joachim Wunderlich , University of Siegen, Germany
Steffen Tarnick , Max-Planck Society, University of Potsdam
pp. 0088

Test Register Insertion with Minimum Hardware Cost (Abstract)

Albrecht P. Stroele , University of Karlsruhe
Hans-Joachim Wunderlich , University of Siegen, Germany
pp. 0095

Pseudo-Random Testing and Signature Analysis for Mixed-Signal Circuits (Abstract)

Chen-Yang Pan , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 0102
Session 2C: New Directions in Circuit Simulation and Verification, Moderators: Peter Feldmann, Andrew T. Yang

Efficient and Accurate Transient Simulation in Charge-Voltage Plane (Abstract)

Anirudh Devgan , IBM Thomas J. Watson Research Center
pp. 0110

A Fast Wavelet Collocation Method for High-Speed VLSI Circuit Simulation (Abstract)

D. Zhou , University of North Carolina at Charlotte
N. Chen , University of North Carolina at Charlotte
W. Cai , The University of California, Santa Barbara
pp. 0115

A Formal Approach to Nonlinear Analog Circuit Verification (Abstract)

Lars Hedrich , University of Hanover
Erich Barke , University of Hanover
pp. 0123
Session 2D: Interconnect Optimization, Moderators: Jason Kong, Georges Gielen

Constrained Multivariable Optimization of Transmission Lines With General Topologies (Abstract)

Rohini Gupta , The University of Texas at Austin
Lawrence T. Pileggi , The University of Texas at Austin
pp. 0130

Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model (Abstract)

John Lillis , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Ting-Ting Y. Lin , University of California, San Diego
pp. 0138

A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing (Abstract)

Noel Menezes , The University of Texas at Austin
Ross Baldick , The University of Texas at Austin
Lawrence T. Pileggi , The University of Texas at Austin
pp. 0144
Session 3A: Decision Diagrams: Applications and Extensions, Moderators: Olivier Coudert, Srinivas Devadas

High Density Reachability Analysis (Abstract)

Kavita Ravi , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 0154

Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs (Abstract)

E.M. Clarke , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Fujita , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
X. Zhao , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0159

Synthesizing Petri Nets from State-Based Models (Abstract)

Jordi Cortadella , Universitat Politecnica de Catalunya
Michael Kishinevsky , The University of Aizu
Luciano Lavagno , Politecnico di Torino
Alex Yakovlev , University of Newcastle upon Tyne
pp. 0164
Session 3B: Fault and Error Diagnosis, Moderators: Wolfgang Kunz, Dhiraj K. Pradhan

Design Verification via Simulation and Automatic Test Pattern Generation (Abstract)

Hussain Al-Asaad , University of Michigan
John P. Hayes , University of Michigan
pp. 0174

On Adaptive Diagnostic Test Generation (Abstract)

Yiming Gong , State University of New York
Sreejit Chakravarty , State University of New York
pp. 0181

Diagnosis of realistic bridging faults with single stuck-at information (Abstract)

B. Chess , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
D.B. Lavo , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
F.J. Ferguson , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
T. Larrabee , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 0185
Session 3C: Substrate Coupling, Moderators: Jue-Hsien Chern, Jacob K. White

Extraction of Circuit Models for Substrate Cross-talk (Abstract)

T. Smedes , Delft University of Technology
N.P. van der Meijs , Delft University of Technology
A.J. Van Genderen , Delft University of Technology
pp. 0199

Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms (Abstract)

Kevin J. Kerns , University of Washington
Ivan L. Wemple , University of Washington
Andrew T. Yang , University of Washington
pp. 0207
Session 3D: Circuit Partitioning, Moderators: Jason Cong, Frank M. Johannes

New algorithms for min-cut replication in partitioned circuits (Abstract)

H.H. Yang , Intel Corp., Hillsboro, OR, USA
D.F. Wong , Intel Corp., Hillsboro, OR, USA
pp. 0216

Linear Decomposition Algorithm for VLSI Design Applications (Abstract)

Jianmin Li , University of California, San Diego
John Lillis , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
pp. 0223

A Gradient Method on the Initial Partition of Fiduccia-Mattheyses Algorithm (Abstract)

Lung-Tien Liu , AT&T Bell Laboratories
Ming-Ter Kuo , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Shih-Chen Huang , New York University
pp. 0229
Session 4A: Embedded Tutorial, Moderator: Gary Hachtel
Session 4B: Embedded Tutorial, Moderator: John Cohn

Coping with RC(L) Interconnect Design Headaches (Abstract)

Lawrence T. Pileggi , The University of Texas at Austin
pp. 0246
Session 5A: Advances in Logic Synthesis, Moderators: Robert Brayton, Gary Hachtel

Logic Decomposition During Technology Mapping (Abstract)

Eric Lehman , Digital Equipment Corporation
Yosinori Watanabe , Digital Equipment Corporation
Joel Grodstein , Digital Equipment Corporation
Heather Harkness , Digital Equipment Corporation
pp. 0264

Efficient Use of Large Don't Cares in High-Level and Logic Synthesis (Abstract)

Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center
Daniel Brand , IBM T. J. Watson Research Center
Leon Stok , IBM T. J. Watson Research Center
Michel Berkelaar , Eindhoven University of Technology
Shiv Prakash , Mentor Graphics Corp.
pp. 0272
Session 5B: System Integration and Debugging, Moderators: Luciano Lavagno, Paul Lippens

Interface co-synthesis techniques for embedded systems (Abstract)

Pai Chou , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
R.B. Ortega , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 0280

Communication synthesis for distributed embedded systems (Abstract)

Ti-Yen Yen , Quickturn Design Syst. Inc., Mountain View, CA, USA
W. Wolf , Quickturn Design Syst. Inc., Mountain View, CA, USA
pp. 0288

Design-for-Debugging of application specific designs (Abstract)

M. Potkonjak , C&C Res. Labs., NEC USA, Princeton, NJ, USA
S. Dey , C&C Res. Labs., NEC USA, Princeton, NJ, USA
K. Wakabayashi , C&C Res. Labs., NEC USA, Princeton, NJ, USA
pp. 0295
Session 5C: Test Generation and Synthesis for Test, Moderators: Fadi Maamari, Irith Pomeranz

A Single-Path-Oriented Fault-Effect Propagation in Digital Circuits Considering Multiple--Path Sensitization (Abstract)

M. Henftling , Technical University of Munich
H. C. Wittmann , Technical University of Munich
Kurt J. Antreich , Technical University of Munich
pp. 0304

Acceleration Techniques for Dynamic Vector Compaction (Abstract)

Anand Raghunathan , Princeton University
Srimat T. Chakradhar , C & C Research Laboratories, NEC USA
pp. 0310

LOT: Logic optimization with testability - new transformations using recursive learning (Abstract)

M. Chatterjee , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W. Kunz , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 0318
Session 5D: FPGA Routing, Moderators: Dwight Hill, Y. Kajitani

An Empirical Model For Accurate Estimation of Routing Delay in FPGAs (Abstract)

Tanay Karnik , University of Illinois
Sung-Mo Kang , University of Illinois
pp. 0328

Performance-driven simultaneous place and route for island-style FPGAs (Abstract)

S.K. Nag , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0332

Board-Level Multi-Terminal Net Routing for FPGA-based Logic Emulation (Abstract)

Wai-Kei Mak , University of Texas at Austin
D.F. Wong , University of Texas at Austin
pp. 0339
, Moderators: Session 6A: FPGA Synthesis, Moderators: Bob Francis, Albert Wang

Technology Mapping for Field-Programmable Gate Arrays Using Integer Programming (Abstract)

Amit Chowdhary , University of Michigan, Ann Arbor, MI
John P. Hayes , University of Michigan, Ann Arbor, MI
pp. 0346

Logic Synthesis for Look-Up Table based FPGAs using Functional Decomposition and Support Minimization (Abstract)

Hiroshi Sawada , NTT Communication Science Laboratories
Takayuki Suyama , NTT Communication Science Laboratories
Akira Nagoya , NTT Communication Science Laboratories
pp. 0353

Compatible Class Encoding in Roth-Karp Decomposition for Two-Output LUT Architecture (Abstract)

Juinn-Dar Huang , National Chiao Tung University
Jing-Yang Jou , National Chiao Tung University
Wen-Zen Shen , National Chiao Tung University
pp. 0359
Session 6B: Circuit Path Analysis in Timing and Power, Moderators: Tom Szymanski, Alexander Saldanha

Estimation of Maximum Transition Counts at Internal Nodes in CMOS VLSI Circuits (Abstract)

Chin-Chi Teng , University of Illinois at Urbana-Champaign
Anthony M. Hill , University of Illinois at Urbana-Champaign
Sung-Mo Kang , University of Illinois at Urbana-Champaign
pp. 0366

Hierarchical Timing Analysis Using Conditional Delays (Abstract)

Hakan Yalcin , University of Michigan
John P. Hayes , University of Michigan
pp. 0371

Timing Analysis with Known False Sub Graphs (Abstract)

Krishna Belkhale , Ambit Design Systems
Alexander J. Suess , IBM, East Fishkill Facility
pp. 736
Session 6C: Code Generation and Performance Estimation, Moderators: Hiroto Yasuura, Wayne Wolf

Performance Estimation of Embedded Software with Instruction Cache Modeling (Abstract)

Yau-Tsun Steven Li , Princeton University
Sharad Malik , Princeton University
Andrew Wolfe , Princeton University
pp. 0380

Memory Bank and Register Allocation in Software Synthesis for ASIPs (Abstract)

Ashok Sudarsanam , Princeton University
Sharad Malik , Princeton University
pp. 0388
Session 6D: Discrete Simulation, Moderators: Steve Tjiang, Robert French

Fast functional simulation using branching programs (Abstract)

P. Ashar , CCRL, NEC USA, Princeton, NJ, USA
S. Malik , CCRL, NEC USA, Princeton, NJ, USA
pp. 0408

Gate-Level Simulation of Digital Circuits Using Multi-Valued Boolean Algebras (Abstract)

Giorgio Casinovi , Georgia Institute of Technology
Scott Woods , Georgia Institute of Technology
pp. 0413
Session 7A: Power and Delay Optimization in Synthesis, Moderators: Sujit Dey, Michel Berkelaar

An Iterative Gate Sizing Approach with Accurate Delay Evaluation (Abstract)

Guangqiu Chen , Kyoto University
Hidetoshi Onodera , Kyoto University
Keikichi Tamaru , Kyoto University
pp. 0422

Boolean Techniques for Low Power Driven Re-Synthesis (Abstract)

R. Iris Bahar , University of Colorado
Fabio Somenzi , University of Colorado
pp. 0428

Two-level logic minimization for low power (Abstract)

S. Iman , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 0433
Session 7B: System-Level Partitioning Issues, Moderators: Jef Van Meerbergen, Rajesh Gupta

PARAS: System-Level Concurrent Partitioning and Scheduling (Abstract)

Wing Hang Wong , University of Wisconsin
Rajiv Jain , University of Wisconsin
pp. 0440

Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques (Abstract)

M. Potkonjak , C&C Res. Labs., NEC USA, Princeton, NJ, USA
W. Wolf , C&C Res. Labs., NEC USA, Princeton, NJ, USA
pp. 0446

System partitioning to maximize sleep time (Abstract)

A.H. Farrahi , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 0452
Session 7C: Gate Sizing, Moderators: Hidetoshi Onodera, Patrick McGeer

A delay model for logic synthesis of continuously-sized networks (Abstract)

J. Grodstein , Digital Equipment Corp., Hudson, MA, USA
E. Lehman , Digital Equipment Corp., Hudson, MA, USA
H. Harkness , Digital Equipment Corp., Hudson, MA, USA
B. Grundmann , Digital Equipment Corp., Hudson, MA, USA
Y. Watanabe , Digital Equipment Corp., Hudson, MA, USA
pp. 0458

Power vs. delay in gate sizing: conflicting objectives? (Abstract)

S.S. Sapatnekar , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Weitong Chuang , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 0463

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization (Abstract)

H. Sathyamurthy , Mentor Graphics, San Jose, CA, USA
S.S. Sapatnekar , Mentor Graphics, San Jose, CA, USA
J.P. Fishburn , Mentor Graphics, San Jose, CA, USA
pp. 0467
Session 7D: Floorplanning and Placement, Moderators: Takashi Kambe, Ralph Otten

Rectangle-Packing-Based Module Placement (Abstract)

H. Murata , Japan Advanced Institute of Science and Technology (JAIST)
K. Fujiyoshi , Japan Advanced Institute of Science and Technology (JAIST)
S. Nakatake , Japan Advanced Institute of Science and Technology (JAIST)
Y. Kajitani , Tokyo Institute of Technology (Titech)
pp. 0472

Re-engineering of timing constrained placements for regular architectures (Abstract)

A. Mathur , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
K.C. Chen , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 0485
Session 8A Embedded Tutorial, Moderator: Sharad Malik

Power Estimation Techniques for Integrated Circuits (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
pp. 0492
Session 8B: Embedded Tutorial, Moderator: Wayne Wolf

CAD challenges in multimedia computing (Abstract)

P. Lippens , Philips Res. Lab., Eindhoven, Netherlands
V. Nagasamy , Philips Res. Lab., Eindhoven, Netherlands
W. Wolf , Philips Res. Lab., Eindhoven, Netherlands
pp. 0502
Session 9A: Memory System Design, Moderators: Nikil Dutt, Don MacMillan

Address Generation for Memories Containing Multiple Arrays (Abstract)

Herman Schmit , Carnegie Mellon University
Donald E. Thomas , Carnegie Mellon University
pp. 0510

Architectural partitioning of control memory for application specific programmable processors (Abstract)

Wei Zhao , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
C.A. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 0521
Session 9B: Novel Views on DFT, Moderators: Wojciech Maly, John P. Hayes

Cost-Free Scan: A Low-Overhead Scan Path Design Methodology (Abstract)

Chih-chang Lin , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Mike Tien-Chien Lee , Fujitsu Laboratories of America, Inc.
Kuang-Chien Chen , Fujitsu Laboratories of America, Inc.
pp. 0528

A Controller-Based Design-for-Testability Technique for Controller-Data Path Circuits (Abstract)

Sujit Dey , C&C Research Laboratories, NEC USA
Vijay Gangaram , C&C Research Laboratories, NEC USA
Miodrag Potkonjak , C&C Research Laboratories, NEC USA
pp. 0534

On Testable Multipliers for Fixed-Width Data Path Architectures (Abstract)

Nilanjan Mukherjee , McGill University
Jerzy Tyszer , McGill University
Janusz Rajski , Mentor Graphics Corporation
pp. 0541
Session 9C: Analog CAD, Moderators: Rob A. Rutenbar, Kurt J. Antreich

A High-Level Design and Optimization Tool for Analog RF Receiver Front-Ends (Abstract)

Jan Crols , Katholieke Universiteit Leuven, ESAT-MICAS
Steaphane Donnay , Katholieke Universiteit Leuven, ESAT-MICAS
Michiel Steyaert , Katholieke Universiteit Leuven, ESAT-MICAS
Georges Gielen , Katholieke Universiteit Leuven, ESAT-MICAS
pp. 0550

A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters (Abstract)

S.R. Kadivar , Res. & Dev., Siemens AG, Munich, Germany
D. Schmitt-Landsiedel , Res. & Dev., Siemens AG, Munich, Germany
H. Klar , Res. & Dev., Siemens AG, Munich, Germany
pp. 0554

Statistical Behavioral Modeling and Characterization of A/D Converters (Abstract)

E.J. Peralias , (CNM), University of Seville
A. Rueda , (CNM), University of Seville
J.L. Huertas , (CNM), University of Seville
pp. 0562
Session 9D: Optimization of Interconnects, Moderators: Majid Sarrafzadeh, Andrew B. Kahng

Optimal Wiresizing for Interconnects with Multiple Sources (Abstract)

Jason Cong , University of California, Los Angeles, CA
Lei He , University of California, Los Angeles, CA
pp. 0568

Post Routing Performance Optimization via Multi-Link Insertion and Non-Uniform Wiresizing (Abstract)

Tianxiong Xue , University of California at Berkeley
Ernest S. Kuh , University of California at Berkeley
pp. 0575

Single-Layer Fanout Routing and Routability Analysis for Ball Grid Arrays (Abstract)

Man-Fai Yu , University of California, Santa Cruz,
Wayne Wei-Ming Dai , University of California, Santa Cruz,
pp. 0581
Session 10A: Advanced Scheduling Techniques, Moderators: Wolfgang Rosenstiel, Yukihiro Nakamura

Time-Constrained Loop Pipelining (Abstract)

Fermin Sanchez , Univ. Politecnica de Catalunya, Barcelona (Spain)
Jordi Cortadella , Univ. Politecnica de Catalunya, Barcelona (Spain)
pp. 0592

An Iterative Improvement Algorithm for Low Power Data Path Synthesis (Abstract)

Anand Raghunathan , Princeton University
Niraj K. Jha , Princeton University
pp. 0597
Session 10B: Sequential Synthesis, Moderators: Luciano Lavagno, Pabio Somenzi

Sequential Synthesis Using S1S (Abstract)

Adnan Aziz , University of California at Berkeley
Felice Balarin , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 0612

Multi-level logic optimization of FSM networks (Abstract)

Huey-Yih Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 0728
Session 10C: Analog Testing, Moderators: Peter C. Maxwell, Kwang-Ting Cheng

Design Based Analog Testing by Characteristic Observation Inference (Abstract)

Walter M. Lindermeir , Technical University of Munich
Helmut E. Graeb , Technical University of Munich
Kurt J. Antreich , Technical University of Munich
pp. 0620

Dynamic Test Signal Design for Analog ICs (Abstract)

Giri Devarayanadurg , University of Washington
Mani Soma , University of Washington
pp. 0627

Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis (Abstract)

Chauchin Su , National Central University
Shenshung Chiang , National Central University
Shyh-Jye Jou , National Central University
pp. 0631
Session 10D: Partitioning for Performance and Power, Moderators: Rajeev Jayaraman, Andrew B. Kahng

Delay optimal partitioning targeting low power VLSI circuits (Abstract)

H. Vaishnav , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 0638

Circuit Partitioning with Logic Perturbation (Abstract)

David Ihsin Cheng , University of California, Santa Barbara
Chih-chang Lin , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 0650
Session 11A: New Objectives in High Level Synthesis, Moderators: Youn-Long Lin, Reinaldo Bergamaschi

Phantom redundancy: a high-level synthesis approach for manufacturability (Abstract)

B. Iyer , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
R. Karri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 0658

APPlaUSE: Area and Performance Optimization in a Unified Placement and Synthesis Environment (Abstract)

Elof Frank , GMD -- German National Research Center for Information Technology
Thomas Lengauer , GMD -- German National Research Center for Information Technology
pp. 0662

Synthesis of multiplier-less FIR filters with minimum number of additions (Abstract)

M. Mehendale , Texas Instrum. (India) Ltd., Bangalore, India
S.D. Sherlekar , Texas Instrum. (India) Ltd., Bangalore, India
G. Venkatesh , Texas Instrum. (India) Ltd., Bangalore, India
pp. 0668
Session 11B: Fault Simulation and Delay Testing, Moderators: Janak H. Patel, Chen-Shang Lin

Functional test generation for delay faults in combinational circuits (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 0687
Session 11C: Circuit Models and TCAD, Moderators: Sani Nassig, Jacob K. White

A Novel Methodology for Statistical Parameter Extraction (Abstract)

Kannan Krishna , Carnegie Mellon University
pp. 0696

Relaxation-Based Harmonic Balance Technique for Semiconductor Device Simulation (Abstract)

Boris Troyanovsky , Stanford University
Zhiping Yu , Stanford University
Lydia So , Stanford University
Robert W. Dutton , Stanford University
pp. 0700

Partitioning and Reduction of RC Interconnect Networks Based on Scattering Parameter Macromodels (Abstract)

Haifang Liao , Ultima Interconnect Technology, Inc.
Wayne Wei-Ming Dai , University of California
pp. 0704
Session 11D: Floorplanning and Placement Algorithms, Moderators: Majid Sarrafiadeh, Ralph Otten

A Unified Approach to Topology Generation and Area Optimization of General Floorplans (Abstract)

Partha S. Dasgupta , Indian Institute of Management
Susmita Sur-Kolay , Jadavpur University
Bhargab B. Bhattacharya , Indian Statistical Institute, Calcutta
pp. 0712

A Timing-driven Data Path Layout Synthesis with Integer Programming (Abstract)

Jaewon Kim , University of Illinois at Urbana-Champaign
S. M. Kang , University of Illinois at Urbana-Champaign
pp. 0716

Signal Integrity Optimization on the Pad Assignment for High-Speed VLSI Design (Abstract)

Kai-Yuan Chao , Intel Corporation
D.F. Wong , University of Texas at Austin
pp. 0720
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