The Community for Technology Leaders
Computer-Aided Design, International Conference on (1995)
San Jose, CA
Nov. 5, 1995 to Nov. 9, 1995
ISBN: 0-8186-7213-7
TABLE OF CONTENTS

Efficient validity checking for processor verification (Abstract)

R.B. Jones , Comput. Syst. Lab., Stanford Univ., CA, USA
D.L. Dill , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 2-6

The formal verification of a pipelined double-precision IEEE floating-point multiplier (Abstract)

M.D. Aagaard , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
C.-J.H. Seger , Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 7-10

Extracting RTL models from transistor netlists (Abstract)

K.J. Singh , AT&T Bell Labs., Holmdel, NJ, USA
P.A. Subrahmanyam , AT&T Bell Labs., Holmdel, NJ, USA
pp. 11-17

Switching activity analysis using Boolean approximation method (Abstract)

T. Uchino , Toshiba Corp., Kawasaki, Japan
F. Minami , Toshiba Corp., Kawasaki, Japan
T. Mitsuhashi , Toshiba Corp., Kawasaki, Japan
pp. 20-25

Estimation and bounding of energy consumption in burst-mode control circuits (Abstract)

P.A. Beerel , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 26-33

Statistical estimation of sequential circuit activity (Abstract)

T.-L. Chou , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 34-37

Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect (Abstract)

M. Chou , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 40-44

Addressing high frequency effects in VLSI interconnects with full wave model and CFH (Abstract)

R. Achar , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
M.S. Nakhla , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Q.J. Zhang , Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
pp. 53-56

Clock distribution design and verification for PowerPC microprocessors (Abstract)

S. Ganguly , Somerset Design Center, Motorola Inc., Austin, TX, USA
pp. 58-61

Activity-driven clock design for low power circuits (Abstract)

G.E. Tellez , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
A. Farrahi , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 62-65

Bounded-skew clock and Steiner routing under Elmore delay (Abstract)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
C.-K. Koh , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
C.-W. Albert Tsao , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 66-71

Who are the variables in your neighbourhood (Abstract)

S. Panda , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 74-77

Be careful with don't cares (Abstract)

D. Brand , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.A. Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Stok , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 83-86

Pattern generation for a deterministic BIST scheme (Abstract)

S. Hellebrand , Siegen Univ., Germany
B. Reeb , Siegen Univ., Germany
pp. 88-94

Test register insertion with minimum hardware cost (Abstract)

A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 95-101

Pseudo-random testing and signature analysis for mixed-signal circuits (Abstract)

C.-Y. Pan , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
K.-T. Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 102-107

Efficient and accurate transient simulation in charge-voltage plane (Abstract)

A. Devgan , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 110-114

A fast wavelet collocation method for high-speed VLSI circuit simulation (Abstract)

D. Zhou , Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
N. Chen , Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
pp. 115-122

A formal approach to nonlinear analog circuit verification (Abstract)

L. Hedrich , Dept. of Electr. Eng., Hannover Univ., Germany
E. Barke , Dept. of Electr. Eng., Hannover Univ., Germany
pp. 123-127

Constrained multivariable optimization of transmission lines with general topologies (Abstract)

R. Gupta , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 130-137

Optimal wire sizing and buffer insertion for low power and a generalized delay model (Abstract)

J. Lillis , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
C.-K. Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 138-143

A sequential quadratic programming approach to concurrent gate and wire sizing (Abstract)

N. Menezes , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
R. Baldick , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
L.T. Pileggi , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 144-151

High-density reachability analysis (Abstract)

K. Ravi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 154-158

Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs (Abstract)

E.M. Clarke , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 159-163

Synthesizing Petri nets from state-based models (Abstract)

J. Cortadella , Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 164-171

Design verification via simulation and automatic test pattern generation (Abstract)

H. Al-Asaad , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 174-180

On adaptive diagnostic test generation (Abstract)

Y. Gong , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
S. Chakravarty , Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
pp. 181-184

Diagnosis of realistic bridging faults with single stuck-at information (Abstract)

B. Chess , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
D.B. Lavo , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
F.J. Ferguson , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
T. Larrabee , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 185-192

SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits (Abstract)

N.K. Verghese , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.J. Allstot , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 194-198

Extraction of circuit models for substrate cross-talk (Abstract)

T. Smedes , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
N.P. van der Meijs , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. van Genderen , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 199-206

Stable and efficient reduction of substrate model networks using congruence transforms (Abstract)

K.J. Kerns , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
I.L. Wemple , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
A.T. Yang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 207-214

New algorithms for min-cut replication in partitioned circuits (Abstract)

H.H. Yang , Intel Corp., Hillsboro, OR, USA
pp. 216-222

Linear decomposition algorithm for VLSI design applications (Abstract)

J. Li , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
J. Lillis , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
C.-K. Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 223-228

Binary decision diagrams and beyond: enabling technologies for formal verification (Abstract)

R.E. Bryant , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 236-243

Coping with RC(L) interconnect design headaches (Abstract)

L. Pileggi , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 246-253

Logic decomposition during technology mapping (Abstract)

E. Lehman , Digital Equipment Corp., Hudson, MA, USA
Y. Watanabe , Digital Equipment Corp., Hudson, MA, USA
J. Grodstein , Digital Equipment Corp., Hudson, MA, USA
H. Harkness , Digital Equipment Corp., Hudson, MA, USA
pp. 264-271

Efficient use of large don't cares in high-level and logic synthesis (Abstract)

R.A. Bergamaschi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D. Brand , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Stok , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 272-278

Interface co-synthesis techniques for embedded systems (Abstract)

Pai Chou , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
R.B. Ortega , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 280-287

Communication synthesis for distributed embedded systems (Abstract)

Ti-Yen Yen , Quickturn Design Syst. Inc., Mountain View, CA, USA
pp. 288-294

Design-for-Debugging of application specific designs (Abstract)

M. Potkonjak , C&C Res. Labs., NEC USA, Princeton, NJ, USA
S. Dey , C&C Res. Labs., NEC USA, Princeton, NJ, USA
pp. 295-301

A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization (Abstract)

M. Henftling , Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
H.C. Wittmann , Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
K.J. Antreich , Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
pp. 304-309

Acceleration techniques for dynamic vector compaction (Abstract)

A. Raghunathan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 310-317

LOT: Logic optimization with testability - new transformations using recursive learning (Abstract)

M. Chatterjee , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
D.K. Pradhan , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W. Kunz , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 318-325

An empirical model for accurate estimation of routing delay in FPGAs (Abstract)

T. Karnik , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Sung-Mo Kang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 328-331

Performance-driven simultaneous place and route for island-style FPGAs (Abstract)

S.K. Nag , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.A. Rutenbar , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 332-338

Board-level multi-terminal net routing for FPGA-based logic emulation (Abstract)

Wai-Kei Mak , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 339-344

Technology mapping for field-programmable gate arrays using integer programming (Abstract)

A. Chowdhary , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 346-352

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization (Abstract)

H. Sawada , NTT Commun. Sci. Labs., Kyoto, Japan
T. Suyama , NTT Commun. Sci. Labs., Kyoto, Japan
A. Nagoya , NTT Commun. Sci. Labs., Kyoto, Japan
pp. 353-358

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture (Abstract)

Juinn-Dar Huang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Wen-Zen Shen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 359-363

Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits (Abstract)

Chin-Chi Teng , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
A.M. Hill , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Sung-Mo Kang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 366-370

Hierarchical timing analysis using conditional delays (Abstract)

H. Yalcin , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 371-377

Performance estimation of embedded software with instruction cache modeling (Abstract)

Y.T.-S. Li , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 380-387

Memory bank and register allocation in software synthesis for ASIPs (Abstract)

A. Sudarsanam , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 388-392

Instruction selection using binate covering for code size optimization (Abstract)

S. Liao , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 393-399

Fast functional simulation using branching programs (Abstract)

P. Ashar , CCRL, NEC USA, Princeton, NJ, USA
pp. 408-412

Gate-level simulation of digital circuits using multi-valued Boolean algebras (Abstract)

S. Woods , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
G. Casinovi , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 413-419

An iterative gate sizing approach with accurate delay evaluation (Abstract)

Guangqiu Chen , Dept. of Electron. & Commun., Kyoto Univ., Japan
H. Onodera , Dept. of Electron. & Commun., Kyoto Univ., Japan
K. Tamaru , Dept. of Electron. & Commun., Kyoto Univ., Japan
pp. 422-427

Boolean techniques for low power driven re-synthesis (Abstract)

R.I. Bahar , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 428-432

Two-level logic minimization for low power (Abstract)

S. Iman , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 433-438

PARAS: System-level concurrent partitioning and scheduling (Abstract)

Wing Hang Wong , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
R. Jain , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 440-445

System partitioning to maximize sleep time (Abstract)

A.H. Farrahi , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 452-455

A delay model for logic synthesis of continuously-sized networks (Abstract)

J. Grodstein , Digital Equipment Corp., Hudson, MA, USA
E. Lehman , Digital Equipment Corp., Hudson, MA, USA
H. Harkness , Digital Equipment Corp., Hudson, MA, USA
B. Grundmann , Digital Equipment Corp., Hudson, MA, USA
Y. Watanabe , Digital Equipment Corp., Hudson, MA, USA
pp. 458-462

Power vs. delay in gate sizing: conflicting objectives? (Abstract)

S.S. Sapatnekar , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 463-466

Rectangle-packing-based module placement (Abstract)

H. Murata , Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
K. Fujiyoshi , Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
S. Nakatake , Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
pp. 472-479

An optimal algorithm for area minimization of slicing floorplans (Abstract)

Weiping Shi , Dept. of Comput. Sci., North Texas Univ., Denton, TX, USA
pp. 480-484

Re-engineering of timing constrained placements for regular architectures (Abstract)

A. Mathur , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 485-490

Power estimation techniques for integrated circuits (Abstract)

F.N. Najm , Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 492-499

CAD challenges in multimedia computing (Abstract)

P. Lippens , Philips Res. Lab., Eindhoven, Netherlands
pp. 502-508

Address generation for memories containing multiple arrays (Abstract)

H. Schmit , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 510-514

Background memory management for dynamic data structure intensive processing systems (Abstract)

G. de Jong , IMEC, Leuven, Belgium
B. Lin , IMEC, Leuven, Belgium
C. Verdonck , IMEC, Leuven, Belgium
S. Wuytack , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
pp. 515-520

Architectural partitioning of control memory for application specific programmable processors (Abstract)

Wei Zhao , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
C.A. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 521-526

Cost-free scan: a low-overhead scan path design methodology (Abstract)

Chih-Chang Lin , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 528-533

A controller-based design-for-testability technique for controller-data path circuits (Abstract)

S. Dey , C&C Res. Labs., NEC, Princeton, NJ, USA
V. Gangaram , C&C Res. Labs., NEC, Princeton, NJ, USA
M. Potkonjak , C&C Res. Labs., NEC, Princeton, NJ, USA
pp. 534-540

On testable multipliers for fixed-width data path architectures (Abstract)

N. Mukherjee , MACS Lab., McGill Univ., Montreal, Que., Canada
J. Rajski , MACS Lab., McGill Univ., Montreal, Que., Canada
J. Tyszer , MACS Lab., McGill Univ., Montreal, Que., Canada
pp. 541-547

A high-level design and optimization tool for analog RF receiver front-ends (Abstract)

J. Crols , Katholieke Univ., Leuven, Belgium
S. Donnay , Katholieke Univ., Leuven, Belgium
M. Steyaert , Katholieke Univ., Leuven, Belgium
G. Gielen , Katholieke Univ., Leuven, Belgium
pp. 550-553

A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters (Abstract)

S.R. Kadivar , Res. & Dev., Siemens AG, Munich, Germany
D. Schmitt-Landsiedel , Res. & Dev., Siemens AG, Munich, Germany
pp. 554-561

Statistical behavioral modeling and characterization of A/D converters (Abstract)

E.J. Peralias , Centro Nacional de Microelectron., Seville Univ., Spain
A. Rueda , Centro Nacional de Microelectron., Seville Univ., Spain
J.L. Huertas , Centro Nacional de Microelectron., Seville Univ., Spain
pp. 562-566

Optimal wiresizing for interconnects with multiple sources (Abstract)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Lei He , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 568-574

Post routing performance optimization via multi-link insertion and non-uniform wiresizing (Abstract)

Tianxiong Xue , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.S. Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 575-580

Single-layer fanout routing and routability analysis for ball grid arrays (Abstract)

Man-Fai Yu , Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
W. Wei-Ming Dai , Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
pp. 581-586

Push-up scheduling: optimal polynomial-time resource constrained scheduling for multi-dimensional applications (Abstract)

N.L. Passos , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E. Hsing-Mean Sha , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 588-591

Time-constrained loop pipelining (Abstract)

F. Sanchez , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Cortadella , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 592-596

An iterative improvement algorithm for low power data path synthesis (Abstract)

A. Raghunathan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 597-602

Symbolic hazard-free minimization and encoding of asynchronous finite state machines (Abstract)

R.M. Fuhrer , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
pp. 604-611

Sequential synthesis using S1S (Abstract)

A. Aziz , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 612-617

Design based analog testing by characteristic observation inference (Abstract)

W.M. Lindermeir , Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
H.E. Graeb , Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
K.J. Antreich , Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
pp. 620-626

Dynamic test signal design for analog ICs (Abstract)

G. Devarayanadurg , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
M. Soma , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 627-630

Impulse response fault model and fault extraction for functional level analog circuit diagnosis (Abstract)

Chauchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shenshung Chiang , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Jye Jou , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 631-636

Delay optimal partitioning targeting low power VLSI circuits (Abstract)

H. Vaishnav , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 638-643

Circuit partitioning with logic perturbation (Abstract)

D.I. Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Chih-Chang Lin , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 650-655

Phantom redundancy: a high-level synthesis approach for manufacturability (Abstract)

B. Iyer , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
R. Karri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 658-661

APPlaUSE: area and performance optimization in a unified placement and synthesis environment (Abstract)

O. Frank , German Nat. Res. Center for Inf. Technol, St. Augustin, Germany
T. Lengauer , German Nat. Res. Center for Inf. Technol, St. Augustin, Germany
pp. 662-667

A multiple-dominance switch-level model for simulation of short faults (Abstract)

P. Dahlgren , Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
pp. 674-680

Fault emulation: a new approach to fault grading (Abstract)

Kwang-Ting Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Shi-Yu Huang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 681-686

Functional test generation for delay faults in combinational circuits (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 687-694

A novel methodology for statistical parameter extraction (Abstract)

K. Krishna , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S.W. Director , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 696-699

Relaxation-based harmonic balance technique for semiconductor device simulation (Abstract)

B. Troyanovsky , Center for Integrated Syst., Stanford Univ., CA, USA
Zhiping Yu , Center for Integrated Syst., Stanford Univ., CA, USA
L. So , Center for Integrated Syst., Stanford Univ., CA, USA
R.W. Dutton , Center for Integrated Syst., Stanford Univ., CA, USA
pp. 700-703

Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels (Abstract)

Haifang Liao , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
W. Wei-Ming Dai , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 704-709

A timing-driven data path layout synthesis with integer programming (Abstract)

J. Kim , Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
S.M. Kang , Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA
pp. 716-719

Multi-level logic optimization of FSM networks (Abstract)

Huey-Yih Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 728-735

Timing analysis with known false sub graphs (Abstract)

K.P. Belkhale , AMBIT, Sunnyvale, CA, USA
pp. 736-739
Session 9D: Optimization of Interconnects, Moderators: Majid Sarrafzadeh, Andrew B. Kahng

Single-Layer Fanout Routing and Routability Analysis for Ball Grid Arrays (Abstract)

Man-Fai Yu , University of California, Santa Cruz,
Wayne Wei-Ming Dai , University of California, Santa Cruz,
pp. 0581
Session 10A: Advanced Scheduling Techniques, Moderators: Wolfgang Rosenstiel, Yukihiro Nakamura

Time-Constrained Loop Pipelining (Abstract)

Fermin Sanchez , Univ. Politecnica de Catalunya, Barcelona (Spain)
Jordi Cortadella , Univ. Politecnica de Catalunya, Barcelona (Spain)
pp. 0592

An Iterative Improvement Algorithm for Low Power Data Path Synthesis (Abstract)

Anand Raghunathan , Princeton University
Niraj K. Jha , Princeton University
pp. 0597
Session 10B: Sequential Synthesis, Moderators: Luciano Lavagno, Pabio Somenzi

Sequential Synthesis Using S1S (Abstract)

Adnan Aziz , University of California at Berkeley
Felice Balarin , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 0612

Multi-level logic optimization of FSM networks (Abstract)

Huey-Yih Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 0728
Session 10C: Analog Testing, Moderators: Peter C. Maxwell, Kwang-Ting Cheng

Design Based Analog Testing by Characteristic Observation Inference (Abstract)

Walter M. Lindermeir , Technical University of Munich
Helmut E. Graeb , Technical University of Munich
Kurt J. Antreich , Technical University of Munich
pp. 0620

Dynamic Test Signal Design for Analog ICs (Abstract)

Giri Devarayanadurg , University of Washington
Mani Soma , University of Washington
pp. 0627

Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis (Abstract)

Chauchin Su , National Central University
Shenshung Chiang , National Central University
Shyh-Jye Jou , National Central University
pp. 0631
Session 10D: Partitioning for Performance and Power, Moderators: Rajeev Jayaraman, Andrew B. Kahng

Delay optimal partitioning targeting low power VLSI circuits (Abstract)

H. Vaishnav , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 0638

Circuit Partitioning with Logic Perturbation (Abstract)

David Ihsin Cheng , University of California, Santa Barbara
Chih-chang Lin , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 0650
Session 11A: New Objectives in High Level Synthesis, Moderators: Youn-Long Lin, Reinaldo Bergamaschi

Phantom redundancy: a high-level synthesis approach for manufacturability (Abstract)

B. Iyer , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
R. Karri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 0658

APPlaUSE: Area and Performance Optimization in a Unified Placement and Synthesis Environment (Abstract)

Elof Frank , GMD -- German National Research Center for Information Technology
Thomas Lengauer , GMD -- German National Research Center for Information Technology
pp. 0662

Synthesis of multiplier-less FIR filters with minimum number of additions (Abstract)

M. Mehendale , Texas Instrum. (India) Ltd., Bangalore, India
S.D. Sherlekar , Texas Instrum. (India) Ltd., Bangalore, India
G. Venkatesh , Texas Instrum. (India) Ltd., Bangalore, India
pp. 0668
Session 11B: Fault Simulation and Delay Testing, Moderators: Janak H. Patel, Chen-Shang Lin

Functional test generation for delay faults in combinational circuits (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 0687
Session 11C: Circuit Models and TCAD, Moderators: Sani Nassig, Jacob K. White

A Novel Methodology for Statistical Parameter Extraction (Abstract)

Kannan Krishna , Carnegie Mellon University
pp. 0696

Relaxation-Based Harmonic Balance Technique for Semiconductor Device Simulation (Abstract)

Boris Troyanovsky , Stanford University
Zhiping Yu , Stanford University
Lydia So , Stanford University
Robert W. Dutton , Stanford University
pp. 0700

Partitioning and Reduction of RC Interconnect Networks Based on Scattering Parameter Macromodels (Abstract)

Haifang Liao , Ultima Interconnect Technology, Inc.
Wayne Wei-Ming Dai , University of California
pp. 0704
Session 11D: Floorplanning and Placement Algorithms, Moderators: Majid Sarrafiadeh, Ralph Otten

A Unified Approach to Topology Generation and Area Optimization of General Floorplans (Abstract)

Partha S. Dasgupta , Indian Institute of Management
Susmita Sur-Kolay , Jadavpur University
Bhargab B. Bhattacharya , Indian Statistical Institute, Calcutta
pp. 0712

A Timing-driven Data Path Layout Synthesis with Integer Programming (Abstract)

Jaewon Kim , University of Illinois at Urbana-Champaign
S. M. Kang , University of Illinois at Urbana-Champaign
pp. 0716

Signal Integrity Optimization on the Pad Assignment for High-Speed VLSI Design (Abstract)

Kai-Yuan Chao , Intel Corporation
D.F. Wong , University of Texas at Austin
pp. 0720
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