1994 IEEE/ACM International Conference On Computer-aided Design [front matter] (PDF)

Behavioral Synthesis From Research To Production Use (PDF)

Design Solutions And Challenges For Low Power Systems (PDF)

Cad Tools For Mixed-signal Simulation, Synthesis And Layout (PDF)

Digital Circuit Interconnec: Issues, Models, Analysis And Design (PDF)

Future Of ICCAD Teenage Years (PDF)

CAD Profession Facts, Trends And Illusions (PDF)

Perturb And Simplify: Multi-level Boolean Network Optimizer (PDF)

Multi-level Logic Optimization By Implication Analysis (PDF)

Incremental Synthesis (PDF)

Definition And Solution Of The Memory Packing Problem For Field-programmable Systems (PDF)

Integrating Program Transformations In The Memory-based Synthesis Of Image And Video Algorithms (PDF)

Dataflow-driven Memory Allocation For Multi-dimensional Signal Processing Systems (PDF)

Test Generation For Bridging Faults In CMOS ICs Based On Current Monitoring Versus Signal Propagation (PDF)

Iterative simulation-based Genetics + Deterministic Techniques = Complete AtPG (PDF)

Analytical Fault Modeling And Static Test Generation For Analog ICs (PDF)

Efficient Network Flow Based Min-cut Balanced Partitioning (PDF)

Multi-way VLSI Circuit Partitioning Based On Dual Net Representation (PDF)

A General Framework For Vertex Orderings, With Applications To Netlist Clustering (PDF)

Re-encoding Sequential Circuits To Reduce Power Dissipation (PDF)

Precomputation-based Sequential Logic Optimization For Low Power (PDF)

Low Power State Assignment Targeting Two- And Multi-level Logic Implementations (PDF)

Algorithm Selection: A Quantitative Computation-intensive Optimization Approach (PDF)

Adaptation Of Partitioning And High-level Synthesis In Hardware/software Co-synthesis (PDF)

Synthesis Of Concurrent System Interface Modules With Automatic Protocol Conversion Generation (PDF)

An Efficient Procedure For The Synthesis Of Fast Self-testable Controller Structures (PDF)

Test Pattern Generation Based On Arithmetic Operations (PDF)

Random Pattern Testable Logic Synthesis (PDF)

Compression-relaxation: A New Approach To Performance Driven Placement For Regular Architectures (PDF)

A Loosely Coupled Parallel Algorithm For Standard Cell Placement (PDF)

Delay And Area Optimization For Compact Placement By Gate Resizing And Relocation (PDF)

Edge-map: Optimal Performance Driven Technology Mapping for Iterative Lut Based Fpga Designs (PDF)

Maple: A Simultaneous Technology Mapping, Placement, And Global Routing Algorithm For Field-programmable Gate Arrays (PDF)

Universal Logic Gate For Fpga Design (PDF)

Condition Graphs For High-quality Behavioral Synthesis (PDF)

Dynamic Scheduling And Synchronization Synthesis Of Concurrent Digital Systems Under System-level Constraints (PDF)

Comprehensive Lower Bound Estimation From Behavioral Descriptions (PDF)

Fast And Accurate Timing Simulation With Regionwise Quadratic Models Of Mos I-V Characteristics (PDF)

Vlsi Timing Simulation With Selective Dynamic Regionization (PDF)

A New Efficient Approach To Statistical Digital Combinational (PDF)

Simultaneous Driver And Wire Sizing For Performance And Power Optimization* (PDF)

Low-cost Single-layer Clock Trees With Exact Zero Elmore Delay Skew (PDF)

Clock Period Constrained Minimal Buffer Insertion In Clock Trees (PDF)

Efficient Implementation Of Retiming (PDF)

Retiming With Non-zero Clock Skew, Variable Register, and Interconnect Delay (PDF)

Optimal Latch Mapping And Retiming Within A Tree (PDF)

Simulation Of Digital Circuits In The Presence of Uncertainty (PDF)

Fast Transient Power And Noise Estimation For VLSI Circuits (PDF)

The Inversion Algorithm For Digital Simulation (PDF)

Unified Complete Mosfet Model For Analysis Of Digital And Analog Circuits (PDF)

A Precorrected-fft Method For Capacitance Extraction of Complicated 3-D Structures (PDF)

Measurement And Modeling Of MOS Transistor Current Mismatch In Analog IC's (PDF)

Skew Sensitivity Minimization Of Buffered Clock Tree (PDF)

Process-variation-tolerant Clock Skew Minimization (PDF)

A Specified Delay Accomplishing Clock Router Using Multiple Layers (PDF)

Switching Activity Analysis Considering Spatioternporal Correlations (PDF)

Estimation Of Circuit Activity Considering Signal Correlations And Simultaneous Switching (PDF)

A Cell-based Power Estimation In Cmos Combinational Circuits (PDF)

Design Exploration For High-performance Pipelines (PDF)

Simultaneous Functional-unit Binding And Floorplanning (PDF)

Module Selection And Data Format Conversion For Cost-optimal Dsp Synthesis (PDF)

On Testing Delay Faults In Macro-based Combinational Circuits (PDF)

Raft: A Novel Program For Rapid-fire Test And Diagnosis Of Digital Logic For Marginal Delays And Delay Faults (PDF)

A Comprehensive Fault Macromodel For Opamps (PDF)

Channel-driven Global Routing With Consistent Placement * (extended Abstract For ICCAD '94) (PDF)

A New Global Routing Algorithm For FPGAs (PDF)

On The Np-completeness Of Regular 2-d Fpga Routing Architectures And A Novel Solution (PDF)

A Symbolic Method To Reduce Power Consumption Of Circuits Containing False Paths (PDF)

Multi-level Network Optimization For Low Power (PDF)

Lp Based Cell Selection With Constraints Of Timing, Area, And Power Consumption (PDF)

Power Analysis Of Embedded Software: A First Step Towards Software Power Minimization (PDF)

Generating Instruction Sets And Microarchitectures From Applications (PDF)

Register assignrnent through resource classification for ASIP microcode generation (Abstract)

Efficient Small-signal Circuit Analysis And Sensitivity Computations With The Pvl Algorithm (PDF)

Capturing Time-of-flight Delay For Transient Analysis Based On Scattering Parameter Macromodel (PDF)

Rc Interconnect Synthesis-a Moment Fitting Approach (PDF)

Adaptive Cut Line Selection In Min-cut Placement For Large Scale Sea-of-gates Arrays (PDF)

Folding A Stack Of Equal Width Components (PDF)

Area Minimization For Hierarchical Floorplans (PDF)

Multi-Level Synthesis For Safe Replaceability (PDF)

Iterative Algorithms For Formal Verification Of Embedded Real-time Systems (PDF)

Incremental Formal Design Verification (PDF)

Optimization Of Critical Paths In Circuits With Level-sensitive Latches (PDF)

Computing The Entire Active Area /power Consumption Versus Delay Trade-Off Curve For Gate Sizing With A Piecewise Linear Simulator (PDF)

Dynamical Identification Of Critical Paths For Iterative Gate Sizing (PDF)

Built-in Self-test And Fault Diagnosis Of Fully Differential Analogue Circuits (PDF)

A New Built-in Self-test Approach For Digital-to-analog And Analog-to-digital Converters (PDF)

Fault Detection And Input Stimulus Determination For The Testing Of Analog Integrated Circuits Based On Power-supply Current Monitoring (PDF)

An Enhanced Flow Model For Constraint Handling In Hierarchical Multi-view Design Environments (PDF)

On Modeling Top-down VLSI Design (PDF)

A Formal Basis For Design Process Planning And Management (PDF)

Design Of Heterogeneous Ics For Mobile And Personal Communication Systems (PDF)

Embedded Systems Design For Low Energy Consumption (PDF)

Synthesis Of Hazard-free Multi-level Logic Under Multiple-input Changes From Binary Decision Diagrams (PDF)

Performance-driven Synthesis Of Asynchronous Controllers (PDF)

Decomposition Methods For Library Binding Of Speed-independent Asynchronous Designs (PDF)

On Error Correction In Macro-based Circuits (PDF)

Fault Dictionary Compaction By Output Sequence Removal (PDF)

Automatic Test Program Generation For Pipelined Processors (PDF)

Synthesis Of Manufacturable Analog Circuits (PDF)

A Statistical Optimization-based Approach For Automated Sizing Of Analog Cells (PDF)

Time-domain Non-monte Carlo Noise Simulation For Nonlinear Dynamic Circuits With Arbitrary Excitations (PDF)

Improving Over-the-cell Channel Routing In Standard Cell Design (PDF)

Minimum Crosstalk Switchbox Routing (PDF)

Techniques For Crosstalk Avoidance In The Physical Design Of High-performance Digital Systems (PDF)

Efficient Breadth-first Manipulation Of Binary Decision Diagrams (PDF)

Symmetry Detection And Dynamic Variable (PDF)

A Redesign Technique For Combinational Circuits Based On Gate Recomections (PDF)

Non-scan Design-for-testability Of Rt-level Data Paths (PDF)

Selecting Partial Scan Flip-flops For Circuit Partitioning (PDF)

Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection (PDF)

Macrornodeling Of Analog Circuits For Hierarchical Circuit Design (PDF)

Approximate Symbolic Analysis Of Large Analog Integrated Circuits (PDF)

Testing Of Analog Systems Using Behavioral Models And Optimal Experimental Design Techniques (PDF)

Layer Assignment For High-performance Multi-chip Modules (PDF)

The Reproducing Placement Problem With Applications (PDF)

Risa: Accurate And Efficient Placement Routability Modeling (PDF)

A New Approach For Factorizing FSM's (PDF)

Boolean Constrained Encoding: A New Formulation And A Case Study (PDF)

Optimization Of Hierarchical Designs Using Partitioning And Resynthesis (PDF)

Hyhope : A Fast Fault Simulator With Efficient Simulation Of Hypertrophic Faults (PDF)

Fast Timing Simulation Of Transient Faults In Digital Circuits (PDF)

A Fast And Memory-efficient Diagnostic Fault Simulation For Sequential Circuits (PDF)

Timing Uncertainty Analysis For Time-of-flight Systems (PDF)

Provably Correct High-level Timing Analysis Without Path Sensitization (PDF)

A Timing Analysis Algorithm For Circuits With Level-sensitive Latches (PDF)

An Object-oriented Cell Library Manager (PDF)

Reuse Of Design Objects In Cad Frameworks (PDF)

Towards Support For Design Description Languages In EDA Frameworks (PDF)