Information Assurance and Security, International Symposium on (2009)
Aug. 18, 2009 to Aug. 20, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IAS.2009.231
Automatic understanding of events happening at a site is the ultimate goal for many visual surveillance systems. Understanding of events requires that certain lower level computer vision tasks be performed. These include foreground detection, labeling foreground parts, and tracking targets. To achieve these tasks, it is necessary to build background subtraction and foreground tracking in the scene. This paper proposed a hardware-oriental algorithm for background subtraction and foreground tracking. To achieve real-time processing and flexibility, the system is then mapped to a SoC architecture with a single camera. The architecture contains two acceleration units and a programmable micro-processor unit. The usage of micro-processor can provide high flexibility for events understanding in different surveillance by user program. And the proposed accelerator hardware unit is used to increase the entire throughput. Simulation results show that the foreground detection and tracking results are satisfied. Performance of the proposed architecture estimated in terms of the number of clocks is brought forward to justify the real-time processing ability for 30 CIF frames per second.
D. Peng, T. Tsai, C. Lin and G. Chen, "Design and Integration for Background Subtraction and Foreground Tracking Algorithm," Information Assurance and Security, International Symposium on(IAS), Xi'An China, 2009, pp. 181-184.