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High Performance Computing and Grid in Asia Pacific Region, International Conference on (2004)
Omiya Sonic City, Tokyo, Japan
July 20, 2004 to July 22, 2004
ISBN: 0-7695-2138-X
pp: 169-177
Tsutomu Yoshinaga , The University of electro-Communications, Japan
Soichi Shigeta , The University of electro-Communications, Japan
Ben A. Abderazek , The University of electro-Communications, Japan
Masahiro Sowa , The University of electro-Communications, Japan
M. Arsenji , The University of electro-Communications, Japan
ABSTRACT
This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a FIFO queue registers instead of random access registers. Datum is inserted in the queue in produced order scheme and can be reused. We will show that this feature has a profound implication in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed. Our preliminary performance evaluations have shown a significant performance improvement (e.g., 10% to 26% decrease in program size and 6% to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.
INDEX TERMS
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CITATION
Tsutomu Yoshinaga, Soichi Shigeta, Ben A. Abderazek, Masahiro Sowa, M. Arsenji, "Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme", High Performance Computing and Grid in Asia Pacific Region, International Conference on, vol. 00, no. , pp. 169-177, 2004, doi:10.1109/HPCASIA.2004.1324032
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