High Performance Computing and Grid in Asia Pacific Region, International Conference on (2004)
Omiya Sonic City, Tokyo, Japan
July 20, 2004 to July 22, 2004
Liqiang He , Chinese Academy of Sciences, Beijing, China
Zhiyong Liu , Chinese Academy of Sciences, Beijing, China
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle. As the number of competing threads increasing, instruction throughput is largely impacted by fetch policy. In this paper, we first describe an ideal fetch model and then propose a new effective instruction fetch policy for SMT processors based on the ideal model. The basic idea of our new policy is to select two threads with least instructions in the instruction queue and feed as many as the needed number of instructions to every selected thread, up to eight in total. The key advantage of our policy is that it can utilize the fetch bandwidth more effectively than ICOUNT.2.8 policy, so that a significant increasing in IPC can be achieved. Execution-driven simulation results show that IPC improvements obtained is up to 45%, and 17% on average, over the ICOUNT.2.8 fetch policy.
L. He and Z. Liu, "An Effective Instruction Fetch Policy for Simultaneous Multithreaded Processors," High Performance Computing and Grid in Asia Pacific Region, International Conference on(HPCASIA), Omiya Sonic City, Tokyo, Japan, 2004, pp. 162-168.