High Performance Computing and Grid in Asia Pacific Region, International Conference on (1997)
Apr. 28, 1997 to May 2, 1997
Hyong-Shik Kim , Seoul National University
Soonhoi Ha , Seoul National University
Chu Shik Jhon , Seoul National University
Since long latency due to remote memory access or interprocessor communication could be tolerated in multithreaded processing, caching I-structure memory is expected to have less beneficial effect on the performance than caching ordinary data. In this paper, we suggest an organization and an operation scheme of an I-structure cache in frame-based multithreading, and show quantitatively that caching I-structure memory could improve the overall performance, in spite of the latency tolerating property of multithreading. With I-structure caches, the performance impacts are found three-fold: the reduction of average latency, the increase of quantum size, and the enhancement of frame parallelism. Among them, the enhancement of frame parallelism seems most important.
multithreading, I-structure caches, performance impacts, latency-tolerating property, frameparallelism
S. Ha, H. Kim and C. S. Jhon, "Performance Impacts of Caching I-Structure Data on Frame-Based Multithreaded Processing," High Performance Computing and Grid in Asia Pacific Region, International Conference on(HPCASIA), Seoul, Korea, 1997, pp. 24.