Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) (2017)
Austin, Texas, USA
Feb. 4, 2017 to Feb. 8, 2017
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HPCA.2017.23
Optical on-chip communication is considered a promising candidate to overcome latency and energy bottlenecks of electrical interconnects. Although recently proposed hybrid Networks-on-chip (NoCs), which implement both electrical and optical links, improve power efficiency, they often fail to combine these two interconnect technologies efficiently and suffer from considerable laser power overheads caused by high-bandwidth optical links. We argue that these overheads can be avoided by inserting a higher quantity of low-bandwidth optical links in a topology, as this yields lower optical loss and in turn laser power. Moreover, when optimally combined with electrical links for short distances, this can be done without trading off latency. We present the effectiveness of this concept with Lego, our hybrid, mesh-based NoC that provides high power efficiency by utilizing electrical links for local traffic, and low-bandwidth optical links for long distances. Electrical links are placed systematically to outweigh the serialization delay introduced by the optical links, simplify router microarchitecture, and allow to save optical resources. Our routing algorithm always chooses the link that offers the lowest latency and energy. Compared to state-of-the-art proposals, Lego increases throughput-per-watt by at least 40%, and lowers latency by 35% on average for synthetic traffic. On SPLASH-2/PARSEC workloads, Lego improves power efficiency by at least 37% (up to 3.5×).
Optical fiber communication, Power lasers, Delays, Bandwidth, Clocks, Optical resonators, Laser modes
"Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links", 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 265-276, 2017, doi:10.1109/HPCA.2017.23