2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) (2016)
March 12, 2016 to March 16, 2016
Vasileios Karakostas , Barcelona Supercomputing Center
Jayneel Gandhi , University of Wisconsin - Madison
Adrian Cristal , Barcelona Supercomputing Center
Mark D. Hill , University of Wisconsin - Madison
Kathryn S. McKinley , Microsoft Research
Mario Nemirovsky , ICREA at Barcelona Supercomputing Center
Michael M. Swift , University of Wisconsin - Madison
Osman S. Unsal , Barcelona Supercomputing Center
Address translation is fundamental to processor performance. Prior work focused on reducing Translation Lookaside Buffer (TLB) misses to improve performance and energy, whereas we show that even TLB hits consume a significant amount of dynamic energy. To reduce the energy cost of address translation, we first propose Lite, a mechanism that monitors the performance and utility of L1 TLBs, and adaptively changes their sizes with way-disabling. The resulting TLBLite organization opportunistically reduces the dynamic energy spent in address translation by 23% on average with minimal impact on TLB miss cycles. To further reduce the energy and performance overheads of L1 TLBs, we also propose RMMLite that targets the recently proposed Redundant Memory Mappings (RMM) address-translation mechanism. RMM maps most of a process's address space with arbitrarily large ranges of contiguous pages in both virtual and physical address space using a modest number of entries in a range TLB. RMMLite adds to RMM an L1-range TLB and the Lite mechanism. The high hit ratio of the L1-range TLB allows Lite to downsize the L1-page TLBs more aggressively. RMMLite reduces the dynamic energy spent in address translation by 71% on average. Above the near-zero L2 TLB misses from RMM, RMMLite further reduces the overhead from L1 TLB misses by 99%. These proposed designs target current and future energy-efficient memory system design to meet the ever increasing memory demands of applications.
V. Karakostas et al., "Energy-efficient address translation," 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, 2016, pp. 631-643.