Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures (Abstract)
High-performance and energy-efficient mobile web browsing on big/little systems (Abstract)
Skinflint DRAM system: Minimizing DRAM chip writes for low power (Abstract)
Enabling distributed generation powered sustainable high-performance data center (Abstract)
A group-commit mechanism for ROB-based processors implementing the X86 ISA (Abstract)
Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches (Abstract)
Two level bulk preload branch prediction (Abstract)
RECAP: A region-based cure for the common cold (cache) (Abstract)
Navigating heterogeneous processors with market mechanisms (Abstract)
Application-to-core mapping policies to reduce memory system interference in multi-core systems (Abstract)
ECM: Effective Capacity Maximizer for high-performance compressed caching (Abstract)
Modeling performance variation due to cache sharing (Abstract)
Cost effective data center servers (Abstract)
Optimizing Google's warehouse scale computers: The NUMA experience (Abstract)
Runnemede: An architecture for Ubiquitous High-Performance Computing (Abstract)
Exploring high-performance and energy proportional interface for phase change memory systems (Abstract)
Coset coding to extend the lifetime of memory (Abstract)
SCRAP: Architecture for signature-based protection from Code Reuse Attacks (Abstract)
Adaptive Reliability Chipkill Correct (ARCC) (Abstract)
Accelerating write by exploiting PCM asymmetries (Abstract)
Optimizing virtual machine scheduling in NUMA multicore systems (Abstract)
Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound (Abstract)
Power-efficient computing for compute-intensive GPGPU applications (Abstract)
Power-performance co-optimization of throughput core architecture using resistive memory (Abstract)
Reducing GPU offload latency via fine-grained CPU-GPU synchronization (Abstract)
Breaking the on-chip latency barrier using SMART (Abstract)
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (Abstract)
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (Abstract)
Warped register file: A power efficient register file for GPGPUs (Abstract)
Disintegrated control for energy-efficient and heterogeneous memory systems (Abstract)
ESESC: A fast multicore simulator using Time-Based Sampling (Abstract)
How to implement effective prediction and forwarding for fusable dynamic multicore architectures (Abstract)
Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons (Abstract)
Layout-conscious random topologies for HPC off-chip interconnects (Abstract)
Scaling towards kilo-core processors with asymmetric high-radix topologies (Abstract)
Energy-efficient interconnect via Router Parking (Abstract)
In-network traffic regulation for Transactional Memory (Abstract)
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling (Abstract)
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing (Abstract)
Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model (Abstract)
High-speed formal verification of heterogeneous coherence hierarchies (Abstract)
Cache coherence for GPU architectures (Abstract)
The dual-path execution model for efficient GPU control flow (Abstract)
Author index (Abstract)
Table of contents (Abstract)
[Front cover] (Abstract)
MISE: Providing performance predictability and improving fairness in shared main memory systems (Abstract)