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IEEE International Symposium on High-Performance Comp Architecture (2012)
New Orleans, LA, USA
Feb. 25, 2012 to Feb. 29, 2012
ISBN: 978-1-4673-0827-4
TABLE OF CONTENTS
Papers

Table of contents (PDF)

pp. v-vii

[Front matter] (PDF)

pp. i-iv
Papers

MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets (Abstract)

Jinho Suh , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles
Murali Annavaram , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles
Michel Dubois , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles
pp. 1-12

Efficient scrub mechanisms for error-prone emerging memories (Abstract)

Manu Awasthi , University of Utah
Manjunath Shevgoor , University of Utah
Kshitij Sudan , University of Utah
Bipin Rajendran , IBM T.J. Watson Research Center
Rajeev Balasubramonian , University of Utah
Viii Srinivasan , IBM T.J. Watson Research Center
pp. 1-12

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips (Abstract)

Timothy N. Miller , Department of Computer Science and Engineering, The Ohio State University
Xiang Pan , Department of Computer Science and Engineering, The Ohio State University
Renji Thomas , Department of Computer Science and Engineering, The Ohio State University
Naser Sedaghati , Department of Computer Science and Engineering, The Ohio State University
Radu Teodorescu , Department of Computer Science and Engineering, The Ohio State University
pp. 1-12

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads (Abstract)

Niladrish Chatterjee , University of Utah
Rajeev Balasubramonian , University of Utah
Al Davis , University of Utah
pp. 1-12

Balancing DRAM locality and parallelism in shared memory CMP systems (Abstract)

Min Kyu Jeong , Dept. of Electrical and Computer Engineering, The University of Texas at Austin
Doe Hyun Yoon , Intelligent Infrastructure Lab, Hewlett-Packard Labs
Dam Sunwoo , ARM Inc
Mike Sullivan , Dept. of Electrical and Computer Engineering, The University of Texas at Austin
Ikhwan Lee , Dept. of Electrical and Computer Engineering, The University of Texas at Austin
Mattan Erez , Dept. of Electrical and Computer Engineering, The University of Texas at Austin
pp. 1-12

MORSE: Multi-objective reconfigurable self-optimizing memory scheduler (Abstract)

Janani Mukundan , Computer Systems Laboratory, Cornell University, Ithaca, NY, 14850 USA
Jose F. Martinez , Computer Systems Laboratory, Cornell University, Ithaca, NY, 14850 USA
pp. 1-12

The case for GPGPU spatial multitasking (Abstract)

Jacob T. Adriaens , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
Katherine Compton , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
Nam Sung Kim , Department of Electrical and Computer Engineering, University of Wisconsin - Madison
Michael J. Schulte , AMD Research
pp. 1-12

TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture (Abstract)

Jaekyu Lee , School of Computer Science, Georgia Institute of Technology
Hyesoon Kim , School of Computer Science, Georgia Institute of Technology
pp. 1-12

CPU-assisted GPGPU on fused CPU-GPU architectures (Abstract)

Yi Yang , Department of Electrical and Computer Engineering, North Carolina State University
Ping Xiang , Department of Electrical and Computer Engineering, North Carolina State University
Mike Mantor , Graphics Products Group, Advanced Micro Devices
Huiyang Zhou , Department of Electrical and Computer Engineering, North Carolina State University
pp. 1-12

Design, integration and implementation of the DySER hardware accelerator into OpenSPARC (Abstract)

Jesse Benson , Vertical Research Group, University of Wisconsin-Madison
Ryan Cofell , Vertical Research Group, University of Wisconsin-Madison
Chris Frericks , Vertical Research Group, University of Wisconsin-Madison
Chen-Han Ho , Vertical Research Group, University of Wisconsin-Madison
Venkatraman Govindaraju , Vertical Research Group, University of Wisconsin-Madison
Tony Nowatzki , Vertical Research Group, University of Wisconsin-Madison
Karthikeyan Sankaralingam , Vertical Research Group, University of Wisconsin-Madison
pp. 1-12

p-TM: Pessimistic invalidation for scalable lazy hardware transactional memory (Abstract)

Anurag Negi , Chalmers University of Technology, Sweden
Ruben Titos-Gil , Universidad de Murcia, Spain
Manuel E. Acacio , Universidad de Murcia, Spain
Jose M. Garcia , Universidad de Murcia, Spain
Per Stenstrom , Chalmers University of Technology, Sweden
pp. 1-12

BulkSMT: Designing SMT processors for atomic-block execution (Abstract)

Xuehai Qian , University of Illinois at Urbana-Champaign
Benjamin Sahelices , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 1-12

Supporting efficient collective communication in NoCs (Abstract)

Sheng Ma , School of Computer, National University of Defense Technology, Changsha, China
Natalie Enright Jerger , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
Zhiying Wang , School of Computer, National University of Defense Technology, Changsha, China
pp. 1-12

Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications (Abstract)

Yangyang Pan , Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute (RPI)
Guiqiang Dong , Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute (RPI)
Qi Wu , Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute (RPI)
Tong Zhang , Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute (RPI)
pp. 1-10

System-level implications of disaggregated memory (Abstract)

Kevin Lim , HP Labs
Yoshio Turner , HP Labs
Alvin AuYoung , HP Labs
Jichuan Chang , HP Labs
Thomas F. Wenisch , University of Michigan, Ann Arbor
pp. 1-12

Improving write operations in MLC phase change memory (Abstract)

Lei Jiang , Electrical and Computer Engineering Department, University of Pittsburgh
Bo Zhao , Electrical and Computer Engineering Department, University of Pittsburgh
Youtao Zhang , Computer Science Department, University of Pittsburgh
Jun Yang , Electrical and Computer Engineering Department, University of Pittsburgh
Bruce R. Childers , Computer Science Department, University of Pittsburgh
pp. 1-10

Adaptive Set-Granular Cooperative Caching (Abstract)

Dyer Rolan , Computer Architecture Group, Electronic and Systems Department, Universidade da Coruña, Spain
Basilio B. Fraguela , Computer Architecture Group, Electronic and Systems Department, Universidade da Coruña, Spain
Ramon Doallo , Computer Architecture Group, Electronic and Systems Department, Universidade da Coruña, Spain
pp. 1-12

Cache restoration for highly partitioned virtualized systems (Abstract)

David Daly , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Harold W. Cain , IBM Thomas J. Watson Research Center, Yorktown Heights, NY
pp. 1-10

Decoupled dynamic cache segmentation (Abstract)

Samira M. Khan , Department of Computer Science, The University of Texas at San Antonio
Zhe Wang , Department of Computer Science, The University of Texas at San Antonio
Daniel A. Jimenez , Department of Computer Science, The University of Texas at San Antonio
pp. 1-12

Computational sprinting (Abstract)

Arun Raghavan , Department of Computer and Information Science, University of Pennsylvania
Yixin Luo , Department of Electrical Engineering and Computer Science, University of Michigan
Anuj Chandawalla , Department of Electrical Engineering and Computer Science, University of Michigan
Marios Papaefthymiou , Department of Electrical Engineering and Computer Science, University of Michigan
Kevin P. Pipe , Department of Electrical Engineering and Computer Science, University of Michigan
Thomas F. Wenisch , Department of Electrical Engineering and Computer Science, University of Michigan
Milo M. K. Martin , Department of Computer and Information Science, University of Pennsylvania
pp. 1-12

Power balanced pipelines (Abstract)

John Sartori , University of Illinois at Urbana-Champaign
Ben Ahrens , University of Illinois at Urbana-Champaign
Rakesh Kumar , University of Illinois at Urbana-Champaign
pp. 1-12

Flexible register management using reference counting (Abstract)

Steven Battle , Drexel University
Andrew D. Hilton , IBM Corporation
Mark Hempstead , Drexel University
Amir Roth , University of Pennsylvania
pp. 1-12

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture (Abstract)

Guihai Yan , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Yinhe Han , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Xiaowei Li , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Minyi Guo , Department of Computer Science and Engineering, Shanghai Jiao Tong University, China
Xiaoyao Liang , Department of Computer Science and Engineering, Shanghai Jiao Tong University, China
pp. 1-12

JETC: Joint energy thermal and cooling management for memory and CPU subsystems in servers (Abstract)

Raid Ayoub , University of California, San Diego, La Jolla, CA 92093-0404
Rajib Nath , University of California, San Diego, La Jolla, CA 92093-0404
Tajana Rosing , University of California, San Diego, La Jolla, CA 92093-0404
pp. 1-12

Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs (Abstract)

Karthik T. Sundararajan , School of Informatics, University of Edinburgh
Vasileios Porpodas , School of Informatics, University of Edinburgh
Timothy M. Jones , Computer Laboratory, University of Cambridge
Nigel P. Topham , School of Informatics, University of Edinburgh
Bjorn Franke , School of Informatics, University of Edinburgh
pp. 1-12

Dynamically heterogeneous cores through 3D resource pooling (Abstract)

Houman Homayoun , University of California San Diego
Vasileios Kontorinis , University of California San Diego
Amirali Shayan , University of California San Diego
Ta-Wei Lin , University of California San Diego
Dean M. Tullsen , University of California San Diego
pp. 1-12

Architectural support for synchronization-free deterministic parallel programming (Abstract)

Cedomir Segulja , The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto
Tarek S. Abdelrahman , The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto
pp. 1-12

Pacman: Tolerating asymmetric data races with unintrusive hardware (Abstract)

Shanxiang Qi , University of Illinois at Urbana-Champaign
Norimasa Otsuki , University of Illinois at Urbana-Champaign
Lois Orosa Nogueira , University of Illinois at Urbana-Champaign
Abdullah Muzahid , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 1-12

BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks (Abstract)

Yuelu Duan , University of Illinois at Urbana-Champaign
Xing Zhou , University of Illinois at Urbana-Champaign
Wonsun Ahn , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 1-12

Parabix: Boosting the efficiency of text processing on commodity processors (Abstract)

Dan Lin , School of Computing Science, Simon Fraser University
Nigel Medforth , School of Computing Science, Simon Fraser University
Kenneth S. Herdy , School of Computing Science, Simon Fraser University
Arrvindh Shriraman , School of Computing Science, Simon Fraser University
Rob Cameron , School of Computing Science, Simon Fraser University
pp. 1-12

WEST: Cloning data cache behavior using Stochastic Traces (Abstract)

Ganesh Balakrishnan , Dept. of Electrical and Computer Engineering, North Carolina State University
Yan Solihin , Dept. of Electrical and Computer Engineering, North Carolina State University
pp. 1-12

Statistical performance comparisons of computers (Abstract)

Tianshi Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Yunji Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Qi Guo , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Olivier Temam , INRIA, Saclay, France
Yue Wu , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Weiwu Hu , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 1-12

Accelerating business analytics applications (Abstract)

Valentina Salapura , IBM T.J. Watson Research Center, Yorktown Heights, NY 10598-0218, USA
Tejas Karkhanis , IBM T.J. Watson Research Center, Yorktown Heights, NY 10598-0218, USA
Priya Nagpurkar , IBM T.J. Watson Research Center, Yorktown Heights, NY 10598-0218, USA
Jose Moreira , IBM T.J. Watson Research Center, Yorktown Heights, NY 10598-0218, USA
pp. 1-10

Architectural perspectives of future wireless base stations based on the IBM PowerENâ?˘ processor (Abstract)

Augusto Vega , IBM Research Division, Yorktown Heights, NY
Pradip Bose , IBM Research Division, Yorktown Heights, NY
Alper Buyuktosunoglu , IBM Research Division, Yorktown Heights, NY
Jeff Derby , IBM Research Division, Research Triangle Park, NC
Michele Franceschini , IBM Research Division, Yorktown Heights, NY
Charles Johnson , IBM Research Division, Yorktown Heights, NY
Robert Montoye , IBM Research Division, Yorktown Heights, NY
pp. 1-10

Network congestion avoidance through Speculative Reservation (Abstract)

Nan Jiang , Stanford University
Daniel U. Becker , Stanford University
George Michelogiannakis , Stanford University
William J. Dally , Stanford University
pp. 1-12

Network within a network approach to create a scalable high-radix router microarchitecture (Abstract)

Jung Ho Ahn , Dept. of Intelligent, Convergence Systems, Seoul National University
Sungwoo Choo , Dept. of Intelligent, Convergence Systems, Seoul National University
John Kim , Dept. of Computer Science & Web Science Technology Division, KAIST
pp. 1-12

Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip (Abstract)

Sheng Ma , School of Computer, National University of Defense Technology, Changsha, China
Natalie Enright Jerger , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada
Zhiying Wang , School of Computer, National University of Defense Technology, Changsha, China
pp. 1-12

Author index (PDF)

pp. 479-481
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