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HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture (2010)
Bangalore India
Jan. 9, 2010 to Jan. 14, 2010
ISSN: 1530-0897
ISBN: 978-1-4244-5658-1
TABLE OF CONTENTS

Value Based BTB Indexing for indirect jump prediction (PDF)

Muhammad Umar Farooq , John Department of Electrical and Computer Engineering, The University of Texas at Austin
Lei Chen , John Department of Electrical and Computer Engineering, The University of Texas at Austin
Lizy Kurian , John Department of Electrical and Computer Engineering, The University of Texas at Austin
pp. 1-11

Operating system support for overlapping-ISA heterogeneous multi-core architectures (PDF)

Tong Li , Intel Corporation
Paul Brett , Intel Corporation
Rob Knauerhase , Intel Corporation
David Koufaty , Intel Corporation
Dheeraj Reddy , Intel Corporation
Scott Hahn , Intel Corporation
pp. 1-12

Scalable architectural support for trusted software (PDF)

David Champagne , Princeton University
Ruby B. Lee , Princeton University
pp. 1-12

ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (PDF)

Yoongu Kim , Carnegie Mellon University
Dongsu Han , Carnegie Mellon University
Onur Mutlu , Carnegie Mellon University
Mor Harchol-Balter , Carnegie Mellon University
pp. 1-12

Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance (PDF)

Fang Liu , Dept. of Electrical and Computer Engineering, North Carolina State University
Xiaowei Jiang , Dept. of Electrical and Computer Engineering, North Carolina State University
Yan Solihin , Dept. of Electrical and Computer Engineering, North Carolina State University
pp. 1-12

LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores (PDF)

Brian Greskamp , Department of Computer Science, University of Illinois at Urbana-Champaign
Ulya R. Karpuzcu , Department of Computer Science, University of Illinois at Urbana-Champaign
Josep Torrellas , Department of Computer Science, University of Illinois at Urbana-Champaign
pp. 1-12

LiteTM: Reducing transactional state overhead (PDF)

Syed Ali Raza Jafri , School of Electrical and Computer Engineering, Purdue University
Mithuna Thottethodi , School of Electrical and Computer Engineering, Purdue University
T. N. Vijaykumar , School of Electrical and Computer Engineering, Purdue University
pp. 1-12

A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems (PDF)

Dimitris Kaseridis , Department of Electrical and Computer Engineering, The University of Texas at Austin, TX, USA
Jeffrey Stuecheli , IBM Corp., Austin, TX, USA
Jian Chen , Department of Electrical and Computer Engineering, The University of Texas at Austin, TX, USA
Lizy K. John , Department of Electrical and Computer Engineering, The University of Texas at Austin, TX, USA
pp. 1-11

HARE: Hardware assisted reverse execution (PDF)

Ioannis Doudalis , Georgia Institute of Technology
Milos Prvulovic , Georgia Institute of Technology
pp. 1-12

Designing a processor from the ground up to allow voltage/reliability tradeoffs (PDF)

Andrew B. Kahng , ECE Departments, University of California, San Diego, La Jolla, CA 92093-0404
Seokhyeong Kang , ECE Departments, University of California, San Diego, La Jolla, CA 92093-0404
Rakesh Kumar , Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL 61801
John Sartori , Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Urbana, IL 61801
pp. 1-11

IADVS: On-demand performance for interactive applications (PDF)

Mingsong Bi , University of Arizona
Igor Crk , University of Arizona
Chris Gniady , University of Arizona
pp. 1-10

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (PDF)

Guangyu Sun , Pennsylvania State University
Yongsoo Joo , Pennsylvania State University
Yibo Chen , Pennsylvania State University
Dimin Niu , Pennsylvania State University
Yuan Xie , Pennsylvania State University
Yiran Chen , Seagate Technology
Hai Li , Seagate Technology
pp. 1-12

Extreme scale computing: Challenges and opportunities (PDF)

Josep Torrellas , University of Illinois at Urbana-Champaign
Bill Gropp , University of Illinois at Urbana-Champaign
Vivek Sarkar , Rice University
Jaime Moreno , IBM T. J. Watson Research Center
Kunle Olukotun , Stanford University
pp. 1

Is hardware innovation over? (PDF)

Arvind , Computer Science and Artificial Intelligence laboratory, Massachusetts Institute of Technology
pp. 1

Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing (Abstract)

Moinuddin K. Qureshi , IBM T. J. Watson Research Center, Yorktown Heights NY
Michele M. Franceschini , IBM T. J. Watson Research Center, Yorktown Heights NY
Luis A. Lastras-Montano , IBM T. J. Watson Research Center, Yorktown Heights NY
pp. 1-11

Delay-Hiding energy management mechanisms for DRAM (PDF)

Mingsong Bi , University of Arizona
Ran Duan , University of Arizona
Chris Gniady , University of Arizona
pp. 1-10

StimulusCache: Boosting performance of chip multiprocessors with excess cache (PDF)

Hyunjin Lee , Dept. of Computer Science, Univ. of Pittsburgh
Sangyeun Cho , Dept. of Computer Science, Univ. of Pittsburgh
Bruce R. Childers , Dept. of Computer Science, Univ. of Pittsburgh
pp. 1-12

ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture (PDF)

Javier Merino , Computer Architecture Group, University of Cantabria, Santander, Spain
Valentin Puente , Computer Architecture Group, University of Cantabria, Santander, Spain
Jose A. Gregorio , Computer Architecture Group, University of Cantabria, Santander, Spain
pp. 1-10

CHOP: Adaptive filter-based DRAM caching for CMP server platforms (PDF)

Xiaowei Jiang , Dept. of Electrical and Computer Engineering, North Carolina State University
Niti Madan , School of Computing, University of Utah
Li Zhao , Dept. of Electrical and Computer Engineering, North Carolina State University
Mike Upton , Intel Labs, Intel Corporation
Ravishankar Iyer , Intel Labs, Intel Corporation
Srihari Makineni , Intel Labs, Intel Corporation
Donald Newell , Intel Labs, Intel Corporation
Yan Solihin , Dept. of Electrical and Computer Engineering, North Carolina State University
Rajeev Balasubramonian , School of Computing, University of Utah
pp. 1-12

Simple virtual channel allocation for high throughput and high frequency on-chip routers (PDF)

Yi Xu , Dept. of Electrical and Computer Engineering
Bo Zhao , Dept. of Electrical and Computer Engineering
Youtao Zhang , Dept. of Computer Science University of Pittsburgh, Pittsburgh, PA 15621
Jun Yang , Dept. of Electrical and Computer Engineering
pp. 1-11

High performance network virtualization with SR-IOV (PDF)

Yaozu Dong , Intel China Software Center, Shanghai, P.R. China
Xiaowei Yang , Intel China Software Center, Shanghai, P.R. China
Xiaoyong Li , Shanghai Jiao Tong University, Shanghai, P.R. China
Jianhui Li , Intel China Software Center, Shanghai, P.R. China
Kun Tian , Intel China Software Center, Shanghai, P.R. China
Haibing Guan , Shanghai Jiao Tong University, Shanghai, P.R. China
pp. 1-10

DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance (PDF)

Dan Tang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Yungang Bao , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Weiwu Hu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Mingyu Chen , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences
pp. 1-12

Graphite: A distributed parallel simulator for multicores (PDF)

Jason E. Miller , Massachusetts Institute of Technology, Cambridge, MA
Harshad Kasture , Massachusetts Institute of Technology, Cambridge, MA
George Kurian , Massachusetts Institute of Technology, Cambridge, MA
Charles Gruenwald , Massachusetts Institute of Technology, Cambridge, MA
Nathan Beckmann , Massachusetts Institute of Technology, Cambridge, MA
Christopher Celio , Massachusetts Institute of Technology, Cambridge, MA
Jonathan Eastep , Massachusetts Institute of Technology, Cambridge, MA
Anant Agarwal , Massachusetts Institute of Technology, Cambridge, MA
pp. 1-12

Interval simulation: Raising the level of abstraction in architectural simulation (PDF)

Davy Genbrugge , Ghent University, Belgium
Stijn Eyerman , Ghent University, Belgium
Lieven Eeckhout , Ghent University, Belgium
pp. 1-12

COMIC++: A software SVM system for heterogeneous multicore accelerator clusters (PDF)

Jaejin Lee , School of Computer Science and Engineering, Seoul National University, Seoul, Korea
Jun Lee , School of Computer Science and Engineering, Seoul National University, Seoul, Korea
Sangmin Seo , School of Computer Science and Engineering, Seoul National University, Seoul, Korea
Jungwon Kim , School of Computer Science and Engineering, Seoul National University, Seoul, Korea
Seungkyun Kim , School of Computer Science and Engineering, Seoul National University, Seoul, Korea
Zehra Sura , IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA
pp. 1-12

BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution (PDF)

Andrew Hilton , Department of Computer and Information Science, University of Pennsylvania
Amir Roth , Department of Computer and Information Science, University of Pennsylvania
pp. 1-12

SIF: Overcoming the limitations of SIMD devices via implicit permutation (PDF)

Libo Huang , School of Computer, National University of Defense Technology, China
Li Shen , School of Computer, National University of Defense Technology, China
Zhiying Wang , School of Computer, National University of Defense Technology, China
Wei Shi , School of Computer, National University of Defense Technology, China
Nong Xiao , School of Computer, National University of Defense Technology, China
Sheng Ma , School of Computer, National University of Defense Technology, China
pp. 1-12

Handling branches in TLS systems with Multi-Path Execution (PDF)

Polychronis Xekalakis , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Marcelo Cintra , School of Informatics, University of Edinburgh
pp. 1-12

Explaining cache SER anomaly using DUE AVF measurement (PDF)

Arijit Biswas , Intel Corporation
Charles Recchia , Intel Corporation
Shubhendu S. Mukherjee , Intel Corporation
Vinod Ambrose , Intel Corporation
Leo Chan , Intel Corporation
Aamer Jaleel , Intel Corporation
Athanasios E. Papathanasiou , Intel Corporation
Mike Plaster , Intel Corporation
Norbert Seifert , Intel Corporation
pp. 1-12

High-Performance low-vcc in-order core (Abstract)

Jaume Abella , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Pedro Chaparro , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Xavier Vera , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Javier Carretero , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Antonio Gonzalez , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
pp. 1-11

Architecting for power management: The IBM® POWER7™ approach (PDF)

Malcolm Ware , IBM Research Austin
Karthick Rajamani , IBM Research Austin
Michael Floyd , IBM Systems and Technology Group
Bishop Brock , IBM Systems and Technology Group
Juan C Rubio , IBM Research Austin
Freeman Rawson , IBM Research Austin
John B Carter , IBM Research Austin
pp. 1-11

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth (PDF)

Dong Hyuk Woo , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
Nak Hee Seong , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
Dean L. Lewis , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
Hsien-Hsin S. Lee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
pp. 1-12

FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar (PDF)

Yan Pan , Northwestern University 2145 Sheridan Road, Evanston, IL
John Kim , KAIST Daejeon, Korea
Gokhan Memik , Northwestern University 2145 Sheridan Road, Evanston, IL
pp. 1-12

Worth their watts? - an empirical study of datacenter servers (PDF)

Arunchandar Vasan , Tata Consultancy Services Limited, India
Anand Sivasubramaniam , Tata Consultancy Services Limited, India
Vikrant Shimpi , Tata Consultancy Services Limited, India
T. Sivabalan , Tata Consultancy Services Limited, India
Rajesh Subbiah , Tata Consultancy Services Limited, India
pp. 1-10

DMA++: on the fly data realignment for on-chip memories (Abstract)

Nikola Vujic , Barcelona Supercomputing Center, Barcelona, Spain
Marc Gonzalez , Universitat Politecnica de Catalunya, Barcelona, Spain
Felipe Cabarcas , Universidad de Antioquia, Medellin, Colombia
Alex Ramirez , Barcelona Supercomputing Center, Barcelona, Spain
Xavier Martorell , Barcelona Supercomputing Center, Barcelona, Spain
Eduard Ayguade , Barcelona Supercomputing Center, Barcelona, Spain
pp. 1-12

Application performance modeling in a virtualized environment (PDF)

Sajib Kundu , School of Computing & Information Sciences
Raju Rangaswami , School of Computing & Information Sciences
Kaushik Dutta , College of Business Administration
Ming Zhao , School of Computing & Information Sciences
pp. 1-10
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