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HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture (2010)
Bangalore India
Jan. 9, 2010 to Jan. 14, 2010
ISSN: 1530-0897
ISBN: 978-1-4244-5658-1
TABLE OF CONTENTS

Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing (Abstract)

Moinuddin K. Qureshi , IBM T. J. Watson Research Center, Yorktown Heights NY
Michele M. Franceschini , IBM T. J. Watson Research Center, Yorktown Heights NY
Luis A. Lastras-Montano , IBM T. J. Watson Research Center, Yorktown Heights NY
pp. 1-11

High-Performance low-vcc in-order core (Abstract)

Jaume Abella , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Pedro Chaparro , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Xavier Vera , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Javier Carretero , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
Antonio Gonzalez , Intel Barcelona Research Center, Intel Labs Barcelona - UPC
pp. 1-11

DMA++: on the fly data realignment for on-chip memories (Abstract)

Nikola Vujic , Barcelona Supercomputing Center, Barcelona, Spain
Marc Gonzalez , Universitat Politecnica de Catalunya, Barcelona, Spain
Felipe Cabarcas , Universidad de Antioquia, Medellin, Colombia
Alex Ramirez , Barcelona Supercomputing Center, Barcelona, Spain
Xavier Martorell , Barcelona Supercomputing Center, Barcelona, Spain
Eduard Ayguade , Barcelona Supercomputing Center, Barcelona, Spain
pp. 1-12
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