Frontal (PDF)
Session 1 Best paper nominees (PDF)
Voltage emergency prediction: Using signatures to reduce operating margins (PDF)
A low-radix and low-diameter 3D interconnection network design (PDF)
Session 2A Multicore cache architectures (PDF)
Adaptive Spill-Receive for robust high-performance caching in CMPs (PDF)
Design and implementation of software-managed caches for multicores with local memory (PDF)
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects (PDF)
Practical off-chip meta-data for temporal memory streaming (PDF)
Session 2B Reliability (PDF)
Soft error vulnerability aware process variation mitigation (PDF)
Accurate microarchitecture-level fault modeling for studying hardware faults (PDF)
Eliminating microarchitectural dependency from Architectural Vulnerability (PDF)
Panel (joint with PPoPP) (PDF)
Opportunities beyond single-core microprocessors (PDF)
Keynote II (joint with PPoPP) (PDF)
Multi-core demands multi-interfaces (PDF)
Session 3A on-chip networks - I (PDF)
Elastic-buffer flow control for on-chip networks (PDF)
Express Cube Topologies for on-Chip Interconnects (PDF)
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (PDF)
Session 3B processor microarchitecture - I (PDF)
Lightweight predication support for out of order processors (PDF)
Blueshift: Designing processors for timing speculation from the ground up. (PDF)
Session 4A NUCA and 3-D stacked memory hierarchies (PDF)
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (PDF)
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy (PDF)
Session 4B Power/performance-efficient architectures and accelerators (PDF)
Reconciling specialization and flexibility through compound circuits (PDF)
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters (PDF)
Variation-aware dynamic voltage/frequency scaling (PDF)
Bridging the computation gap between programmable processors and hardwired accelerators (PDF)
Industrial perspectives panel (joint with PPoPP) (PDF)
Industrial perspectives panel (PDF)
Session 5A Performance modeling and analysis (PDF)
A first-order fine-grained multithreaded throughput model (PDF)
Characterization of Direct Cache Access on multi-core systems and 10GbE (PDF)
Session 5B On-chip networks - II (PDF)
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks (PDF)
Prediction router: Yet another low latency on-chip router architecture (PDF)
Session 6A Security, verification, and validation (PDF)
Fast complete memory consistency verification (PDF)
Hardware-software integrated approaches to defend against software cache-based side channel attacks (PDF)
Dacota: Post-silicon validation of the memory subsystem in multi-core designs (PDF)
Session 6B processor microarchitecture - II (PDF)
Criticality-based optimizations for efficient load processing (PDF)
iCFP: Tolerating all-level cache misses in in-order processors (PDF)
Feedback mechanisms for improving probabilistic memory prefetching (PDF)
Keynote III (joint with PPoPP) (PDF)