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2008 IEEE 14th International Symposium on High Performance Computer Architecture (2008)
Salt Lake City, UT USA
Feb. 16, 2008 to Feb. 20, 2008
ISSN: 1530-0897
ISBN: 978-1-4244-2070-4
TABLE OF CONTENTS

Information (PDF)

pp. x-xii

Design and implementation of the blue gene/P snoop filter (PDF)

Valentina Salapura , IBM Thomas J. Watson Research Center Yorktown Heights, NY, USA
Matthias Blumrich , IBM Thomas J. Watson Research Center Yorktown Heights, NY, USA
Alan Gara , IBM Thomas J. Watson Research Center Yorktown Heights, NY, USA
pp. 5-14

Prediction of CPU idle-busy activity pattern (PDF)

Qian Diao , Intel Corp., USA
Justin Song , Intel Corp., USA
pp. 27-36

Performance-aware speculation control using wrong path usefulness prediction (PDF)

Chang Joo Lee , Department of Electrical and Computer Engineering The University of Texas at Austin, USA
Hyesoon Kim , School of Computer Science Georgia Institute of Technology, USA
Onur Mutlu , Computer Architecture Group, Microsoft Research, USA
Yale N. Patt , Department of Electrical and Computer Engineering The University of Texas at Austin, USA
pp. 39-49

PaCo: Probability-based path confidence prediction (PDF)

Kshitiz Malik , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA
Mayank Agarwal , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA
Vikram Dhar , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA
Matthew I. Frank , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA
pp. 50-61

Branch-mispredict level parallelism (BLP) for control independence (PDF)

Kshitiz Malik , Coordinated Science Laboratory University of Illinois at Urbana-Champaign, USA
Mayank Agarwal , Coordinated Science Laboratory University of Illinois at Urbana-Champaign, USA
Sam S. Stone , Coordinated Science Laboratory University of Illinois at Urbana-Champaign, USA
Kevin M. Woley , Coordinated Science Laboratory University of Illinois at Urbana-Champaign, USA
Matthew I. Frank , Coordinated Science Laboratory University of Illinois at Urbana-Champaign, USA
pp. 62-73

Address-branch correlation: A novel locality for long-latency hard-to-predict branches (PDF)

Hongliang Gao , School of Electrical Engineering and Computer Science, University of Central Florida, USA
Yi Ma , School of Electrical Engineering and Computer Science, University of Central Florida, USA
Martin Dimitrov , School of Electrical Engineering and Computer Science, University of Central Florida, USA
Huiyang Zhou , School of Electrical Engineering and Computer Science, University of Central Florida, USA
pp. 74-85

EXCES: External caching in energy saving storage systems (PDF)

Luis Useche , School of Computing and Information Sciences, Florida International University, Miami, USA
Jorge Guerra , School of Computing and Information Sciences, Florida International University, Miami, USA
Medha Bhadkamkar , School of Computing and Information Sciences, Florida International University, Miami, USA
Mauricio Alarcon , School of Computing and Information Sciences, Florida International University, Miami, USA
Raju Rangaswami , School of Computing and Information Sciences, Florida International University, Miami, USA
pp. 89-100

Cluster-level feedback power control for performance optimization (PDF)

Xiaorui Wang , Department of Electrical Engineering and Computer Science University of Tennessee, Knoxville, 37996, USA
Ming Chen , Department of Electrical Engineering and Computer Science University of Tennessee, Knoxville, 37996, USA
pp. 101-110

C-Oracle: Predictive thermal management for data centers (PDF)

Luiz Ramos , Department of Computer Science, Rutgers University, USA
Ricardo Bianchini , Department of Computer Science, Rutgers University, USA
pp. 111-122

System level analysis of fast, per-core DVFS using on-chip switching regulators (PDF)

Wonyoung Kim , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
Meeta S. Gupta , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
Gu-Yeon Wei , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
David Brooks , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
pp. 123-134

PEEP: Exploiting predictability of memory dependences in SMT processors (PDF)

Samantika Subramaniam , Georgia Institute of Technology College of Computing, USA
Milos Prvulovic , Georgia Institute of Technology College of Computing, USA
Gabriel H. Loh , Georgia Institute of Technology College of Computing, USA
pp. 137-148

Single-level integrity and confidentiality protection for distributed shared memory multiprocessors (PDF)

Brian Rogers , Dept. of Electrical and Computer Engineering North Carolina State University, USA
Chenyu Yan , College of Computing Georgia Institute of Technology, USA
Siddhartha Chhabra , Dept. of Electrical and Computer Engineering North Carolina State University, USA
Milos Prvulovic , College of Computing Georgia Institute of Technology, USA
Yan Solihin , Dept. of Electrical and Computer Engineering North Carolina State University, USA
pp. 161-172

FlexiTaint: A programmable accelerator for dynamic taint propagation (PDF)

Guru Venkataramani , Georgia Tech, USA
Ioannis Doudalis , Georgia Tech, USA
Yan Solihin , NC State University, USA
Milos Prvulovic , Georgia Tech, USA
pp. 173-184

Amdahl’s Law in the multicore era (PDF)

Mark D. Hill , Computer Sciences Department University of Wisconsin┐Madison, USA
pp. 187

CMP network-on-chip overlaid with multi-band RF-interconnect (PDF)

M. Frank Chang , UCLA Electrical Engineering Department, USA
Jason Cong , UCLA Computer Science Department, USA
Adam Kaplan , UCLA Computer Science Department, USA
Mishali Naik , UCLA Computer Science Department, USA
Glenn Reinman , UCLA Computer Science Department, USA
Eran Socher , UCLA Electrical Engineering Department, USA
Sai-Wang Tam , UCLA Electrical Engineering Department, USA
pp. 191-202

Regional congestion awareness for load balance in networks-on-chip (PDF)

Paul Gratz , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Boris Grot , Department of Computer Sciences, The University of Texas at Austin, USA
Stephen W. Keckler , Department of Computer Sciences, The University of Texas at Austin, USA
pp. 203-214

Performance and power optimization through data compression in Network-on-Chip architectures (PDF)

Reetuparna Das , Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA
Asit K. Mishra , Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA
Chrysostomos Nicopoulos , Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA
Dongkook Park , Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA
Vijaykrishnan Narayanan , Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA
Ravishankar Iyer , Corporate Technology Group, Intel Corporation, Hillsboro, OR 97124, USA
Mazin S. Yousif , Corporate Technology Group, Intel Corporation, Hillsboro, OR 97124, USA
Chita R. Das , Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA
pp. 215-225

Automated microprocessor stressmark generation (PDF)

Ajay M. Joshi , The University of Texas at Austin, USA
Lieven Eeckhout , Ghent University, Belgium
Lizy K. John , The University of Texas at Austin, USA
Ciji Isen , The University of Texas at Austin, USA
pp. 229-239

Roughness of microarchitectural design topologies and its implications for optimization (PDF)

Benjamin C. Lee , School of Engineering and Applied Sciences, Harvard University, USA
David Brooks , School of Engineering and Applied Sciences, Harvard University, USA
pp. 240-251

Fundamental performance constraints in horizontal fusion of in-order cores (PDF)

Pierre Salverda , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
Craig Zilles , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
pp. 252-263

Serializing instructions in system-intensive workloads: Amdahl’s Law strikes again (PDF)

Philip M. Wells , Computer Sciences Department, University of Wisconsin-Madison, USA
Gurindar S. Sohi , Computer Sciences Department, University of Wisconsin-Madison, USA
pp. 264-275

Thread-safe dynamic binary translation using transactional memory (PDF)

JaeWoong Chung , Computer Systems Laboratory, Stanford University, USA
Michael Dalton , Computer Systems Laboratory, Stanford University, USA
Hari Kannan , Computer Systems Laboratory, Stanford University, USA
Christos Kozyrakis , Computer Systems Laboratory, Stanford University, USA
pp. 279-289

Uncovering hidden loop level parallelism in sequential applications (PDF)

Hongtao Zhong , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Mojtaba Mehrara , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Steve Lieberman , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Scott Mahlke , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
pp. 290-301

A comprehensive approach to DRAM power management (PDF)

Ibrahim Hur , IBM Corporation, Systems and Technology Group, Austin, TX, USA
Calvin Lin , The University of Texas at Austin, Department of Computer Sciences, USA
pp. 305-316

Power-Efficient DRAM Speculation (PDF)

Nidhi Aggarwal , Electrical and Computer Engineering Dept. University of Wisconsin, Madison 1415 Engineering Drive Madison, 53705, USA
Jason F. Cantin , International Business Machines Corp. 11400 Burnet Road Austin, TX 78758, USA
Mikko H. Lipasti , Electrical and Computer Engineering Dept. University of Wisconsin, Madison 1415 Engineering Drive Madison, 53705, USA
James E. Smith , Electrical and Computer Engineering Dept. University of Wisconsin, Madison 1415 Engineering Drive Madison, 53705, USA
pp. 317-328

High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation (PDF)

Richard H. Larson , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
John K. Salmon , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Ron O. Dror , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Martin M. Deneroff , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Cliff Young , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
J.P. Grossman , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Yibing Shan , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
John L. Klepeis , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
David E. Shaw , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
pp. 331-342

Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation (PDF)

Jeffrey S. Kuskin , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Cliff Young , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
J.P. Grossman , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Brannon Batson , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Martin M. Deneroff , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
Ron O. Dror , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
David E. Shaw , D. E. Shaw Research, 39th Floor, Tower 45, 120 West 45th Street, New York, 10036, USA
pp. 343-354

An OS-based alternative to full hardware coherence on tiled CMPs (PDF)

Christian Fensch , School of Informatics, University of Edinburgh, UK
Marcelo Cintra , School of Informatics, University of Edinburgh, UK
pp. 355-366

Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems (PDF)

Jiang Lin , Dept. of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
Qingda Lu , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, 43210, USA
Xiaoning Ding , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, 43210, USA
Zhao Zhang , Dept. of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
Xiaodong Zhang , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, 43210, USA
P. Sadayappan , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, 43210, USA
pp. 367-378

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (PDF)

Meeta S. Gupta , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
Krishna K. Rangan , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
Michael D. Smith , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
Gu-Yeon Wei , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
David Brooks , School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, USA
pp. 381-392

Supporting highly-decoupled thread-level redundancy for parallel programs (PDF)

M. Wasiur Rashid , Dept. of Electrical & Computer Engineering, University of Rochester, USA
Michael C. Huang , Dept. of Electrical & Computer Engineering, University of Rochester, USA
pp. 393-404

Speculative instruction validation for performance-reliability trade-off (PDF)

Sumeet Kumar , Electrical and Computer Engineering, Binghamton University, NY 13902, USA
Aneesh Aggarwal , Electrical and Computer Engineering, Binghamton University, NY 13902, USA
pp. 405-414

Runtime validation of memory ordering using constraint graph checking (PDF)

Kaiyu Chen , Dept. of Electrical Engineering, Princeton University, USA
Sharad Malik , Dept. of Electrical Engineering, Princeton University, USA
Priyadarsan Patra , Intel Validation Research Lab, USA
pp. 415-426

Compilers and parallel computing systems (PDF)

Frances Allen , IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Yorktown Heights, NY 10598, USA, 914-945-2769
pp. 429
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