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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2006)
Austin, TX, USA
Feb. 11, 2006 to Feb. 15, 2006
ISSN: 1530-0897
ISBN: 0-7803-9368-6
TABLE OF CONTENTS

Chip-multiprocessing and beyond (PDF)

P. Stenstrom , Chalmers Univ. of Technol., Goteborg, Sweden
pp. 109
Papers

BulletProof: a defect-tolerant CMP switch architecture (Abstract)

J. Blome , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
S. Plaza , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
K. Constantinides , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 5-16

CMP design space exploration subject to physical constraints (Abstract)

null Yingmin Li , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 17-28

An approach for implementing efficient superscalar CISC processors (Abstract)

S. Hu , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 41-52

A decoupled KILO-instruction processor (Abstract)

R. Gonzalez , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Pericas , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
A. Cristal , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 53-64

Store vectors for scalable memory dependence prediction and scheduling (Abstract)

G.H. Loh , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
null Samantika Subramaniam , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 65-76

Dynamic power-performance adaptation of parallel computation on chip multiprocessors (Abstract)

J.F. Martinez , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA
J. Li , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA
pp. 77-87

Construction and use of linear regression models for processor performance analysis (Abstract)

M.J. Thazhuthaveetil , Dept. of Comput. Sci.&Autom., Indian Inst. of Sci., Bangalore, India
null Kapil Vaswani , Dept. of Comput. Sci.&Autom., Indian Inst. of Sci., Bangalore, India
P.J. Joseph , Dept. of Comput. Sci.&Autom., Indian Inst. of Sci., Bangalore, India
pp. 99-108

Probabilistic counter updates for predictor hysteresis and stratification (Abstract)

C. Zilles , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
N. Riley , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 110-120

Phase characterization for power: evaluating control-flow-based and event-counter-based techniques (Abstract)

C. Isci , Dept. of Electr. Eng., Princeton Univ., NJ, USA
M. Martonosi , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 121-132

DMA-aware memory energy management (Abstract)

W. Jiang , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Y. Zhou , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
null Vivek Pandey , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 133-144

Increasing the cache efficiency by eliminating noise (Abstract)

P. Pujara , Dept. of Electr.&Comput. Eng., Binghamton Univ., NY, USA
A. Aggarwal , Dept. of Electr.&Comput. Eng., Binghamton Univ., NY, USA
pp. 145-154

Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM (Abstract)

S. Herr , ECE Dept., North Carolina State Univ., Raleigh, NC, USA
E. Rotenberg , ECE Dept., North Carolina State Univ., Raleigh, NC, USA
R.K. Venkatesan , ECE Dept., North Carolina State Univ., Raleigh, NC, USA
pp. 155-165

Understanding the performance-temperature interactions in disk I/O of server workloads (Abstract)

Youngjae Kim , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 176-186

High performance file I/O for the Blue Gene/L supercomputer (Abstract)

C. Howson , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Almasi , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
J.G. Castanos , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.K. Sahoo , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Gupta , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
H. Yu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 187-196

ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers (Abstract)

P. Montesinos , Illinois Univ., Champaign, IL, USA
J. Nakano , Illinois Univ., Champaign, IL, USA
pp. 200-211

Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors (Abstract)

null Sumeet Kumar , ECE Dept., Binghamton Univ., NY, USA
null Aneesh Aggarwal , ECE Dept., Binghamton Univ., NY, USA
pp. 212-221

CORD: cost-effective (and nearly overhead-free) order-recording and data race detection (Abstract)

M. Prvulovic , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 232-243

Software-hardware cooperative memory disambiguation (Abstract)

R. Huang , Dept. of Electr.&Comput. Eng., Rochester Univ., NY, USA
A. Garg , Dept. of Electr.&Comput. Eng., Rochester Univ., NY, USA
M. Huang , Dept. of Electr.&Comput. Eng., Rochester Univ., NY, USA
pp. 244-253

LogTM: log-based transactional memory (Abstract)

M.J. Moravan , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
D.A. Wood , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
M.D. Hill , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
K.E. Moore , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
J. Bobba , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 254-265

The common case transactional behavior of multithreaded programs (Abstract)

A. McDonald , Comput. Syst. Lab., Stanford Univ., CA, USA
K. Olukotun , Comput. Syst. Lab., Stanford Univ., CA, USA
C.C. Minh , Comput. Syst. Lab., Stanford Univ., CA, USA
J.W. Chung , Comput. Syst. Lab., Stanford Univ., CA, USA
B. Carlstrom , Comput. Syst. Lab., Stanford Univ., CA, USA
H. Chafi , Comput. Syst. Lab., Stanford Univ., CA, USA
C. Kozyrakis , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 266-277

Efficient instruction schedulers for SMT processors (Abstract)

J.J. Sharkey , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
D.V. Ponomarev , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 288-298
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