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The Twelfth International Symposium on High-Performance Computer Architecture, 2006. (2006)
Austin, TX, USA
Feb. 11, 2006 to Feb. 15, 2006
ISSN: 1530-0897
ISBN: 0-7803-9368-6
pp: 254-265
K.E. Moore , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
J. Bobba , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
M.J. Moravan , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
M.D. Hill , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
D.A. Wood , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
ABSTRACT
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes providing data version management for the simultaneous storage of both new (visible if the transaction commits) and old (retained if the transaction aborts) values. Most (hardware) TM systems leave old values "in place" (the target memory address) and buffer new values elsewhere until commit. This makes aborts fast, but penalizes (the much more frequent) commits. In this paper, we present a new implementation of transactional memory, log-based transactional memory (LogTM), that makes commits fast by storing old values to a per-thread log in cacheable virtual memory and storing new values in place. LogTM makes two additional contributions. First, LogTM extends a MOESI directory protocol to enable both fast conflict detection on evicted blocks and fast commit (using lazy cleanup). Second, LogTM handles aborts in (library) software with little performance penalty. Evaluations running micro- and SPLASH-2 benchmarks on a 32-way multiprocessor support our decision to optimize for commit by showing that only 1-2% of transactions abort.
INDEX TERMS
SPLASH-2 benchmark, log-based transactional memory, parallel programming, data version management, cacheable virtual memory, MOESI directory protocol, software library
CITATION

M. Moravan, D. Wood, M. Hill, K. Moore and J. Bobba, "LogTM: log-based transactional memory," The Twelfth International Symposium on High-Performance Computer Architecture, 2006.(HPCA), Austin, TX, USA, 2006, pp. 254-265.
doi:10.1109/HPCA.2006.1598134
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