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The Twelfth International Symposium on High-Performance Computer Architecture, 2006. (2006)
Austin, TX, USA
Feb. 11, 2006 to Feb. 15, 2006
ISSN: 1530-0897
ISBN: 0-7803-9368-6
pp: 155-165
R.K. Venkatesan , ECE Dept., North Carolina State Univ., Raleigh, NC, USA
S. Herr , ECE Dept., North Carolina State Univ., Raleigh, NC, USA
E. Rotenberg , ECE Dept., North Carolina State Univ., Raleigh, NC, USA
ABSTRACT
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention time of a page is defined as the shortest retention time among its constituent cells). Currently, a single worst-case refresh period is selected based on the page with the shortest retention time. Even with refresh optimized for room temperature, the worst page limits the safe refresh period to no longer than 500 ms. Yet, 99% and 85% of pages have retention times above 3 seconds and 10 seconds, respectively. We propose retention-aware placement in DRAM (RAPID), novel software approaches that can exploit off-the-shelf DRAMs to reduce refresh power to vanishingly small levels approaching non-volatile memory. The key idea is to favor longer-retention pages over shorter-retention pages when allocating DRAM pages. This allows selecting a single refresh period that depends on the shortest-retention page among populated pages, instead of the shortest-retention page overall. We explore three versions of RAPID and observe refresh energy savings of 83%, 93%, and 95%, relative to the best temperature-compensated refresh. RAPID with off-the-shelf DRAM also approaches the energy levels of idealized techniques that require custom DRAM support.
INDEX TERMS
shortest retention time, retention-aware placement, software methods, quasinonvolatile DRAM, off-the-shelf DRAM chip, refresh power reduction, worst-case refresh period
CITATION

S. Herr, E. Rotenberg and R. Venkatesan, "Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM," The Twelfth International Symposium on High-Performance Computer Architecture, 2006.(HPCA), Austin, TX, USA, 2006, pp. 155-165.
doi:10.1109/HPCA.2006.1598122
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