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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2005)
San Francisco, California
Feb. 12, 2005 to Feb. 16, 2005
ISSN: 1530-0897
ISBN: 0-7695-2275-0
TABLE OF CONTENTS
Keynote
Session 1: Processor Architecture

Multithreaded Value Prediction (Abstract)

Nathan Tuck , University of California, San Diego
Dean M. Tullsen , University of California, San Diego
pp. 5-15

Checkpointed Early Load Retirement (Abstract)

Jos? F. Mart?nez , Cornell University, Ithaca, NY
Nevin Kirman , Cornell University, Ithaca, NY
Mainak Chaudhuri , Cornell University, Ithaca, NY
Meyrem Kirman , Cornell University, Ithaca, NY
pp. 16-27

A Small, Fast and Low-Power Register File by Bit-Partitioning (Abstract)

Hiroshi Nakamura , The University of Tokyo, Japan
Masaaki Kondo , The University of Tokyo, Japan
pp. 40-49
Session 2: Temperature, Energy, and Power

Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses (Abstract)

Nihar R. Mahapatra , Michigan State University, East Lansing
Krishnan Sundaresan , Michigan State University, East Lansing
pp. 51-60

Distributing the Frontend for Temperature Reduction (Abstract)

Pedro Chaparro , Intel Barcelona Research Center - Intel Labs - UPC
Jos? Gonz?lez , Intel Barcelona Research Center - Intel Labs - UPC
Grigorios Magklis , Intel Barcelona Research Center - Intel Labs - UPC
Antonio Gonz?lez , Intel Barcelona Research Center - Intel Labs - UPC
pp. 61-70

Performance, Energy, and Thermal Considerations for SMT and CMP Architectures (Abstract)

Kevin Skadron , University of Virginia
Yingmin Li , University of Virginia
Zhigang Hu , IBM T.J. Watson Research Center
David Brooks , Harvard University
pp. 71-82

Tapping ZettaRAM™ for Low-Power Memory Systems (Abstract)

Ravi K. Venkatesan , North Carolina State University
Eric Rotenberg , North Carolina State University
Ahmed S. AL-Zawawi , North Carolina State University
pp. 83-94
Session 3: Communication Architectures

An Efficient Programmable 10 Gigabit Ethernet Network Interface Card (Abstract)

Paul Willmann , Rice University, Houston, TX
Vijay S. Pai , Purdue University, West Lafayette, IN
Scott Rixner , Rice University, Houston, TX
Hyong-youb Kim , Rice University, Houston, TX
pp. 96-107

A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks (Abstract)

J. Duato , Tech. Univ. of Valencia, Spain
J. Flich , Tech. Univ. of Valencia, Spain
I. Johnson , Xyratex, United Kingdom
F. Naven , Xyratex, United Kingdom
P. Garc? , Univ. of Castilla-La Mancha, Spain
T. Nachiondo , Tech. Univ. of Valencia, Spain
pp. 108-119

Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems (Abstract)

Li-Shiuan Peh , Princeton University, NJ
Gu-Yeon Wei , Harvard University, Cambridge, MA
Xuning Chen , Princeton University, NJ
Paul Prucnal , Princeton University, NJ
Yue-Kai Huang , Princeton University, NJ
pp. 120-131

Scatter-Add in Data Parallel Architectures (Abstract)

Jung Ho Ahn , Stanford University, CA
William J. Dally , Stanford University, CA
Mattan Erez , Stanford University, CA
pp. 132-142
Session 4: Energy and Power

Software Directed Issue Queue Power Reduction (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya
Timothy M. Jones , University of Edinburgh, UK
Michael F. P. O'Boyle , University of Edinburgh, UK
Jaume Abella , Universitat Polit?cnica de Catalunya
pp. 144-153

On the Limits of Leakage Power Reduction in Caches (Abstract)

Timothy Sherwood , University of California, Santa Barbara
Yan Meng , University of California, Santa Barbara
Ryan Kastner , University of California, Santa Barbara
pp. 154-165

Heat Stroke: Power-Density-Based Denial of Service in SMT (Abstract)

Jahangir Hasan , Purdue University
T. N. Vijaykumar , Purdue University
Ankit Jalote , Purdue University
Carla E. Brodley , Tufts University
pp. 166-177

Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (Abstract)

Philo Juang , Princeton University
Margaret Martonosi , Princeton University
Douglas W. Clark , Princeton University
Qiang Wu , Princeton University
pp. 178-189
Session 5: Memory System Issues

Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions (Abstract)

Aamer Jaleel , University of Maryland, College Park
Bruce Jacob , University of Maryland, College Park
pp. 191-200

A Unified Compressed Memory Hierarchy (Abstract)

Steven K. Reinhardt , University of Michigan
Erik G. Hallnor , University of Michigan
pp. 201-212

A Performance Comparison of DRAM Memory System Optimizations for SMT Processors (Abstract)

Zhichun Zhu , University of Illinois at Chicago
Zhao Zhang , Iowa State University
pp. 213-224

Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications (Abstract)

Santosh G. Abraham , Sun Microsystems Inc., Sunnyvale, CA
Lawrence Spracklen , Sun Microsystems Inc., Sunnyvale, CA
Yuan Chou , Sun Microsystems Inc., Sunnyvale, CA
pp. 225-236
Session 6: Industrial Perspectives (I)

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors (Abstract)

Hans Jacobson , IBM T.J Watson Research Center
Doug Logan , IBM Systems and Technology Group
Rick Eickemeyer , IBM Systems and Technology Group
Joel Tendler , IBM Systems and Technology Group
Balaram Sinharoy , IBM Systems and Technology Group
Lee Eisen , IBM Systems and Technology Group
Pradip Bose , IBM T.J Watson Research Center
John Griswell , IBM Systems and Technology Group
Alper Buyuktosunoglu , IBM T.J Watson Research Center
Zhigang Hu , IBM T.J Watson Research Center
Victor Zyuban , IBM T.J Watson Research Center
pp. 238-242

The Soft Error Problem: An Architectural Perspective (Abstract)

Steven K. Reinhardt , University of Michigan, Ann Arbor
Joel Emer , Intel Corporation, Hudson MA
Shubhendu S. Mukherjee , Intel Corporation, Hudson MA
pp. 243-247

Chip Multithreading: Opportunities and Challenges (Abstract)

Lawrence Spracklen , Sun Microsystems Inc., Sunnyvale, CA
Santosh G. Abraham , Sun Microsystems Inc., Sunnyvale, CA
pp. 248-252

Enterprise IT Trends and Implications for Architecture Research (Abstract)

Parthasarathy Ranganathan , ISSL/MMSL, Hewlett Packard Labs, Palo Alto, USA
Norman Jouppi , ISSL/MMSL, Hewlett Packard Labs, Palo Alto, USA
pp. 253-256
Session 7: Industrial Perspectives (II)

Power Efficient Processor Architecture and The Cell Processor (Abstract)

H. Peter Hofstee , IBM Server & Technology Group
pp. 258-262
Panel: New Opportunities for Computer Architecture Research: An Industrial Perspective
Session 8: Evaluation Methodologies

Characterizing and Comparing Prevailing Simulation Techniques (Abstract)

David J. Lilja , University of Minnesota, Minneapolis, MN
Resit Sendag , University of Rhode Island, Kingston, RI
Sreekumar V. Kodakara , University of Minnesota, Minneapolis, MN
Douglas M. Hawkins , University of Minnesota, Minneapolis, MN
Joshua J. Yi , Freescale Semiconductor, Inc., Austin, TX
pp. 266-277

Transition Phase Classification and Prediction (Abstract)

Jeremy Lau , University of California, San Diego
Brad Calder , University of California, San Diego
Stefan Schoenmackers , University of California, San Diego
pp. 278-289
Session 9: Software Debugging Support

SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs (Abstract)

Yuanyuan Zhou , University of Illinois at Urbana Champaign
Shan Lu , University of Illinois at Urbana Champaign
Feng Qin , University of Illinois at Urbana Champaign
pp. 291-302

Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE (Abstract)

E Christopher Lewis , University of Pennsylvania, Philadelphia
Amir Roth , University of Pennsylvania, Philadelphia
Marc L. Corliss , University of Pennsylvania, Philadelphia
pp. 303-314
Session 10: Multiprocessors and Multithreading

Unbounded Transactional Memory (Abstract)

Bradley C. Kuszmaul , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Sean Lie , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
C. Scott Ananian , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Krste Asanovic , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Charles E. Leiserson , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
pp. 316-327

Improving Multiple-CMP Systems Using Token Coherence (Abstract)

Milo M. K. Martin , University of Pennsylvania
Jesse D. Bingham , University of British Columbia
Alan J. Hu , University of British Columbia
David A. Wood , University of Wisconsin-Madison
Mark D. Hill , University of Wisconsin-Madison
Michael R. Marty , University of Wisconsin-Madison
pp. 328-339

Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture (Abstract)

Dhruba Chandra , North Carolina State University
Fei Guo , North Carolina State University
Yan Solihin , North Carolina State University
Seongbeom Kim , North Carolina State University
pp. 340-351

SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors (Abstract)

Jun Yang , University of California at Riverside
Youtao Zhang , University of Texas at Dallas
Xiangyu Zhang , University of Arizona, Tucson
Rajiv Gupta , University of Arizona, Tucson
Lan Gao , University of California at Riverside
pp. 352-362

Author Index (PDF)

pp. 363
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