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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2004)
Madrid, Spain
Feb. 14, 2004 to Feb. 18, 2004
ISSN: 1530-0897
ISBN: 0-7695-2053-7
TABLE OF CONTENTS
Introduction

list-reviewer (PDF)

pp. xi
Keynote I

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pp. null
Session 1: Power Management

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pp. null

Exploiting Prediction to Reduce Power on Buses (Abstract)

Yatish Patel , University of California at Berkeley
Mark Whitney , University of California at Berkeley
John D. Kubiatowicz , University of California at Berkeley
Victor Wen , University of California at Berkeley
pp. 2

The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors (Abstract)

José F. Martínez , Cornell University
Jian Li , Cornell University
Michael C. Huang , University of Rochester
pp. 14

Program Counter Based Techniques for Dynamic Power Management (Abstract)

Chris Gniady , Purdue University
Y Charlie Hu , Purdue University
Yung-Hsiang Lu , Purdue University
pp. 24
Session 2: Processor Design I

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pp. null

Out-of-Order Commit Processors (Abstract)

Mateo Valero , Universidad Politécnica de Cataluña
Adrian Cristal , Universidad Politécnica de Cataluña
Josep Llosa , Universidad Politécnica de Cataluña
Daniel Ortega , Hewlett Packard Labs
pp. 48

Stream Register Files with Indexed Access (Abstract)

Jung Ho Ahn , Stanford University
William J. Dally , Stanford University
Nuwan Jayasena , Stanford University
Mattan Erez , Stanford University
pp. 60

Low-Complexity Distributed Issue Queue (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya and Intel Barcelona Research Center
Jaume Abella , Universitat Polit?cnica de Catalunya
pp. 73
Session 3: Prefetching

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pp. null

Hardware Support for Prescient Instruction Prefetch (Abstract)

Paul Chow , University of Toronto
Per Hammarlund , Intel Corporation
Tor M. Aamodt , University of Toronto
John P. Shen , Intel Corporation
Hong Wang , Intel Corporation
pp. 84

Data Cache Prefetching Using a Global History Buffer (Abstract)

James E. Smith , University of Wisconsin - Madison
Kyle J. Nesbit , University of Wisconsin - Madison
pp. 96

Processor Aware Anticipatory Prefetching in Loops (Abstract)

Mahadevan Rajagopalan , Sun Microsystems, Inc.
Vikram Rao , Sun Microsystems, Inc.
Partha Tirumalai , Sun Microsystems, Inc.
Spiros Kalogeropulos , Sun Microsystems, Inc.
Yonghong Song , Sun Microsystems, Inc.
pp. 106
Panel Session:
Keynote II

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pp. null
Session 4: I/O

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pp. null

Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management (Abstract)

Yuanyuan Zhou , University of Illinois at Urbana Champaign
Qingbo Zhu , University of Illinois at Urbana Champaign
Zhenmin Li , University of Illinois at Urbana Champaign
Pei Cao , Cisco Systems Inc.
Francis M. David , University of Illinois at Urbana Champaign
Christo F. Devaraj , University of Illinois at Urbana Champaign
pp. 118

Improving Disk Throughput in Data-Intensive Servers (Abstract)

Ricardo Bianchini , Rutgers University
Enrique V. Carrera , Rutgers University
pp. 130

Synthesizing Representative I/O Workloads for TPC-H (Abstract)

Jianyong Zhang , Pennsylvania State University
Yanyong Zhang , Rutgers University
Hubertus Franke , IBM T. J. Watson Research Center
Anand Sivasubramaniam , Pennsylvania State University
Natarajan Gautam , Pennsylvania State University
Shailabh Nagar , IBM T. J. Watson Research Center
pp. 142
Session 5: Caches & Memory I

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pp. null

Signature Buffer: Bridging Performance Gap between Registers and Caches (Abstract)

Lu Peng , University of Florida
Konrad Lai , Intel Corporation
Jih-Kwon Peir , University of Florida
pp. 164

Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs (Abstract)

Chun Liu , Pennsylvania State University
Anand Sivasubramaniam , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
pp. 176
Keynote III

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pp. null
Session 6: Scheduling

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pp. null

Understanding Scheduling Replay Schemes (Abstract)

Mikko H. Lipasti , University of Wisconsin-Madison
Ilhyun Kim , University of Wisconsin-Madison
pp. 198

Creating Converged Trace Schedules Using String Matching (Abstract)

Suleyman Sair , North Carolina State University
Yuanfang Hu , University of California at San Diego
Brad Calder , University of California at San Diego
Satish Narayanasamy , University of California at San Diego
pp. 210

Reducing the Scheduling Critical Cycle Using Wakeup Prediction (Abstract)

Todd E. Ehrhart , University of Illinois at Urbana-Champaign
Sanjay J. Patel , University of Illinois at Urbana-Champaign
pp. 222

Exploring Wakeup-Free Instruction Scheduling (Abstract)

Jie S. Hu , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
pp. 232
Keynote IV

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pp. null
Session 7: Processor Design II

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pp. null

A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors (Abstract)

Ayose Falcón , Universitat Politècnica de Catalunya
Mateo Valero , Universitat Politècnica de Catalunya
Alex Ramirez , Universitat Politècnica de Catalunya
pp. 244

Reducing Branch Misprediction Penalty via Selective Branch Recovery (Abstract)

Srikanth T. Srinivasan , Intel Corporation
Amit Gandhi , Intel Corporation and Portland State University
Haitham Akkary , Intel Corporation and Portland State University
pp. 254

Perceptron-Based Branch Confidence Estimation (Abstract)

Rajendar Koltur , Portland State University
Wael Refaai , Portland State University
Srikanth T. Srinivasan , Intel Corporation
Yogesh Patil , Portland State University
Haitham Akkary , Portland State University and Intel Corporation
pp. 265
Session 8: Caches & Memory II

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pp. null

Accurate and Complexity-Effective Spatial Pattern Prediction (Abstract)

Chi F. Chen , Carnegie Mellon University
Babak Falsafi , Carnegie Mellon University
Andreas Moshovos , University of Toronto
Se-Hyun Yang , Carnegie Mellon University
pp. 276

Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses (Abstract)

Jaejin Lee , Seoul National University
Yan Solihin , North Carolina State University
Mazen Kharbutli , North Carolina State University
Keith Irwin , North Carolina State University
pp. 288

Link-Time Path-Sensitive Memory Redundancy Elimination (Abstract)

Roger Espasa , Universitat Politècnica de Catalunya
Manel Fernández , Universitat Politècnica de Catalunya
pp. 300
Author Index

Author Index (PDF)

pp. 311
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