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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2003)
Anaheim, California
Feb. 8, 2003 to Feb. 12, 2003
ISSN: 1530-0897
ISBN: 0-7695-1871-0
TABLE OF CONTENTS
Introduction

Reviewers (PDF)

pp. xiii
Keynote Speaker
Multithreading

Variability in Architectural Simulations of Multi-Threaded Workloads (Abstract)

David A. Wood , University of Wisconsin-Madison
Alaa R. Alameldeen , University of Wisconsin-Madison
pp. 7

Mini-Threads: Increasing TLP on Small-Scale SMT Processors (Abstract)

Susan Eggers , University of Washington
Henry Levy , University of Washington
Joshua Redstone , University of Washington
pp. 19

Front-End Policies for Improved Issue Efficiency in SMT Processors (Abstract)

David H. Albonesi , University of Rochester
Ali El-Moursy , University of Rochester
pp. 31
Branch Prediction

Incorporating Predicate Information into Branch Predictors (Abstract)

Jeanne Ferrante , University of California at San Diego
Brad Calder , University of California at San Diego
Beth Simon , University of San Diego
pp. 53

Dynamic Data Dependence Tracking and its Application to Branch Prediction (Abstract)

Steve Dropsho , University of Rochester
David H. Albonesi , University of Rochester
Lei Chen , University of Rochester
pp. 65
Power Efficient Designs

Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (Abstract)

Russ Joseph , Princeton University
David Brooks , Harvard University
Margaret Martonosi , Princeton University
pp. 79

Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks (Abstract)

Li Shang , Princeton University
Li-Shiuan Peh , Princeton University
Niraj K. Jha , Princeton University
pp. 91

Power-Aware Control Speculation through Selective Throttling (Abstract)

José González , Intel Labs
Antonio González , Intel Labs and Universitat Polit?cnica de Catalunya
Juan L. Aragón , Universidad de Murcia
pp. 103

Deterministic Clock Gating for Microprocessor Power Reduction (Abstract)

Swarup Bhunia , Purdue University
Kaushik Roy , Purdue University
T. N. Vijaykumar , Purdue University
Hai Li , Purdue University
Yiran Chen , Purdue University
pp. 113
Keynote Speaker
Superscalars

Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors (Abstract)

Jared Stark , Intel Labs
Yale N. Patt , University ofTexas at Austin
Onur Mutlu , University ofTexas at Austin
Chris Wilkerson , Intel Corporation
pp. 129

Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems (Abstract)

Haruhiko Ueno , Fujitsu Limited
Yasunori Kimura , Fujitsu Laboritories LTD.
Mariko Sakamoto , Fujitsu Laboritories LTD.
Takeo Asakawa , Fujitsu Limited
Akira Katsuno , Fujitsu Laboritories LTD.
Aiichiro Inoue , Fujitsu Limited
Kuniki Morita , Fujitsu Limited
pp. 141

Exploring the VLSI Scalability of Stream Processors (Abstract)

John D. Owens , Stanford University
Brucek Khailany , Stanford University
William J. Dally , Stanford University
Scott Rixner , Rice University
Brian Towles , Stanford University
Ujval J. Kapasi , Stanford University
pp. 153

Dynamic Optimization of Micro-Operations (Abstract)

Brian Fahs , University of Illinois at Urbana-Champaign
Gregory Muthler , University of Illinois at Urbana-Champaign
Brian Slechta , University of Illinois at Urbana-Champaign
Francesco Spadini , University of Illinois at Urbana-Champaign
Steven S. Lumetta , University of Illinois at Urbana-Champaign
David Crowe , University of Illinois at Urbana-Champaign
Justin Quek , University of Illinois at Urbana-Champaign
Michael Fertig , University of Illinois at Urbana-Champaign
Sanjay J. Patel , University of Illinois at Urbana-Champaign
pp. 165
Multiprocessor Systems

Slipstream Execution Mode for CMP-Based Multiprocessors (Abstract)

Eric Rotenberg , North Carolina State University
Gregory T. Byrd , North Carolina State University
Khaled Z. Ibrahim , North Carolina State University
pp. 179

Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors (Abstract)

José María Llabería , Universitat Politècnica de Catalunya
Milos Prvulovic , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
Víctor Viñals , Universidad de Zaragoza
Lawrence Rauchwerger , Texas A&M University
María Jesús Garzarán , Universidad de Zaragoza
pp. 191
Memory and Communication Performance

Memory System Behavior of Java-Based Middleware (Abstract)

Martin Karlsson , Uppsala University
David A. Wood , University of Wisconsin
Kevin E. Moore , University of Wisconsin
Erik Hagersten , Uppsala University
pp. 217

Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services (Abstract)

Kiran Nagaraja , Rutgers University
Ricardo Bianchini , Rutgers University
Thu D. Nguyen , Rutgers University
Richard P. Martin , Rutgers University
Neeraj Krishnan , Rutgers University
pp. 229

Performance Enhancement Techniques for InfiniBand™ Architecture (Abstract)

Eun Jung Kim , Pennsylvania State University
Mazin Yousif , Intel Corporation
José Duato , Universidad Politécnica de Valencia
Ki Hwan Yum , University of Texas at San Antonio
Chita R. Das , Pennsylvania State University
pp. 253
Keynote Speaker

The State of State (PDF)

Peter M. Kogge , University of Notre Dame
pp. 266
Profiling and Simulation Support

Catching Accurate Profiles in Hardware (Abstract)

Satish Narayanasamy , University of California at San Diego
George Varghese , University of California at San Diego
Suleyman Sair , University of California at San Diego
Timothy Sherwood , University of California at San Diego
Brad Calder , University of California at San Diego
pp. 269

A Statistically Rigorous Approach for Improving Simulation Methodology (Abstract)

Douglas M. Hawkins , University of Minnesota — Twin Cities
David J. Lilja , University of Minnesota — Twin Cities
Joshua J. Yi , University of Minnesota — Twin Cities
pp. 281
Caching and Prefetching

Caches and Hash Trees for Efficient Memory Integrity Verification (Abstract)

G.Edward Suh , Massachusetts Institute of Technology
Blaise Gassend , Massachusetts Institute of Technology
Srinivas Devadas , Massachusetts Institute of Technology
Marten van Dijk , Massachusetts Institute of Technology
Dwaine Clarke , Massachusetts Institute of Technology
pp. 295

Just Say No: Benefits of Early Cache Miss Determination (Abstract)

Glenn Reinman , University of California at Los Angeles
Gokhan Memik , University of California at Los Angeles
William H. Mangione-Smith , University of California at Los Angeles
pp. 307

TCP: Tag Correlating Prefetchers (Abstract)

Stefanos Kaxiras , Agere Systems
Margaret Martonosi , Princeton University
Zhigang Hu , IBM Corporation
pp. 317

Cost-Sensitive Cache Replacement Algorithms (Abstract)

Michel Dubois , University of Southern California
pp. 327
Networks and Communication

Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures (Abstract)

Walter Lee , Massachusetts Institute of Technology
Anant Agarwal , Massachusetts Institute of Technology
Michael Bedford Taylor , Massachusetts Institute of Technology
Saman Amarasinghe , Massachusetts Institute of Technology
pp. 341

Inter-Cluster Communication Models for Clustered VLIW Processors (Abstract)

Manish Garg , Philips Research
Erwan Le Thenaff , Philips Research
Henk Corporaal , IMEC and Technical University of Eindhoven
Jos van Eijndhoven , Philips Research
Andrei Terechko , Philips Research
pp. 354

Active I/O Switches in System Area Networks (Abstract)

Mark Heinrich , University of Central Florida
Ming Hao , Cornell University
pp. 365

A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns (Abstract)

Timothy Mark Pinkston , University of Southern California
Wai Hong Ho , University of Southern California
pp. 377
Author Index

Author Index (PDF)

pp. 389
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