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The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. (2003)
Anaheim, California
Feb. 8, 2003 to Feb. 12, 2003
ISSN: 1530-0897
ISBN: 0-7695-1871-0
pp: 295
Blaise Gassend , Massachusetts Institute of Technology
G.Edward Suh , Massachusetts Institute of Technology
Dwaine Clarke , Massachusetts Institute of Technology
Marten van Dijk , Massachusetts Institute of Technology
Srinivas Devadas , Massachusetts Institute of Technology
ABSTRACT
<p>We study the hardware cost f implementing hash-tree based verification of untrusted external memory by a high performance processor.This verification could enable applications such as certified program execution.</p> <p>A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the performance overhead is less than 25%, a significant decrease from the 10? overhead of a naive implementation.</p>
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CITATION

G. Suh, B. Gassend, S. Devadas, M. van Dijk and D. Clarke, "Caches and Hash Trees for Efficient Memory Integrity Verification," The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.(HPCA), Anaheim, California, 2003, pp. 295.
doi:10.1109/HPCA.2003.1183547
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