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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2002)
Boston, Massachusettes
Feb. 2, 2002 to Feb. 6, 2002
ISBN: 0-7695-1525-8
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Keynote Speaker
Energy and Thermal Management I

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (Abstract)

Greg Semeraro , University of Rochester
Grigorios Magklis , University of Rochester
Rajeev Balasubramonian , University of Rochester
David H. Albonesi , University of Rochester
Sandhya Dwarkadas , University of Rochester
Michael L. Scott , University of Rochester
pp. 0029

Thread-Spawning Schemes for Speculative Multithreading (Abstract)

Pedro Marcuello , Universitat Polit?cnica de Catalunya
Antonio González , Universitat Polit?cnica de Catalunya
pp. 0055

Improving Value Communication for Thread-Level Speculation (Abstract)

J. Gregory Steffan , Carnegie Mellon University
Christopher B. Colohan , Carnegie Mellon University
Antonia Zhai , Carnegie Mellon University
Todd C. Mowry , Carnegie Mellon University
pp. 0065
Panel
Potpourri

Tuning Garbage Collection in an Embedded Java Environment (Abstract)

G. Chen , The Pennsylvania State University
R. Shetty , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
M.J. Irwin , The Pennsylvania State University
M. Wolczko , Sun Microsystems, Inc.
pp. 0092
Memory-Aware Scheduling

Fine-grain Priority Scheduling on Multi-channel Memory Systems (Abstract)

Zhichun Zhu , College of William and Mary
Zhao Zhang , College of William and Mary
Xiaodong Zhang , College of William and Mary
pp. 0107
Energy and Thermal Management II

The Minimax Cache: An Energy-Efficient Framework for Media Processors (Abstract)

Osman S. Unsal , University of Massachusetts
Israel Koren , University of Massachusetts
C. Mani Krishna , University of Massachusetts
Csaba Andras Moritz , University of Massachusetts
pp. 0131

Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach (Abstract)

Sudhanva Gurumurthi , The Pennsylvania State University
Anand Sivasubramaniam , The Pennsylvania State University
Mary Jane Irwin , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
Mahmut Kandemir , The Pennsylvania State University
Tao Li , University of Texas at Austin
Lizy Kurian John , University of Texas at Austin
pp. 0141

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay (Abstract)

Se-Hyun Yang , Carnegie Mellon University
Babak Falsafi , Carnegie Mellon University
Michael D. Powell , Purdue University
T. N. Vijaykumar , Purdue University
pp. 0151
Latency Tolerance and Caches

Non-vital Loads (Abstract)

Ryan Rakvic , Intel Corporation
Bryan Black , Carnegie Mellon University
Deepak Limaye , Carnegie Mellon University
John P. Shen , Carnegie Mellon University
pp. 0165

Let's Study Whole-Program Cache Behaviour Analytically (Abstract)

Xavier Vera , Malardalens Hogskola
Jingling Xue , University of New South Wales
pp. 0175

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs.Speculative Precomputation (Abstract)

Perry H. Wang , Intel Corporation
Hong Wang , Intel Corporation
Jamison D. Collins , Intel Corporation
Ed Grochowski , Intel Corporation
Ralph M. Kling , Intel Corporation
John P. Shen , Intel Corporation
pp. 0187

Quantifying Load Stream Behavior (Abstract)

Suleyman Sair , University of California, San Diego
Timothy Sherwood , University of California, San Diego
Brad Calder , University of California, San Diego
pp. 0197
Speculation and Prediction

Modeling Value Speculation (Abstract)

Yiannakis Sazeides , University of Cyprus
pp. 0211

The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches (Abstract)

Martin Kampe , Chalmers University of Technology
Per Stenstrom , Chalmers University of Technology
Michel Dubois , University of Southern California
pp. 0223

Power Issues Related to Branch Prediction (Abstract)

Dharmesh Parikh , Univeristy Of Virginia
Kevin Skadron , Univeristy Of Virginia
Yan Zhang , Univeristy Of Virginia
Marco Barcella , Univeristy Of Virginia
Mircea R. Stan , Univeristy Of Virginia
pp. 0233
Keynote Speaker
Multiprocessor Systems

Bandwidth Adaptive Snooping (Abstract)

Milo M. K. Martin , University of Wisconsin-Madison
Daniel J. Sorin , University of Wisconsin-Madison
Mark D. Hill , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
pp. 0251

User-Level Communication in Cluster-Based Servers (Abstract)

Enrique V. Carrera , Rutgers University
Srinath Rao , Rutgers University
Liviu Iftode , Rutgers University
Ricardo Bianchini , Rutgers University
pp. 0275
Pipelining and Microarchitecture

Loose Loops Sink Chips (Abstract)

Eric Borch , Intel
Joel Emer , Intel
Eric Tune , University of California, San Diego
pp. 0299

Evaluation of a Multithreaded Architecture for Cellular Computing (Abstract)

Calin Cascaval , IBM Thomas J. Watson Research Center
Jose G. Castanos , IBM Thomas J. Watson Research Center
Luis Ceze , IBM Thomas J. Watson Research Center
Monty Denneau , IBM Thomas J. Watson Research Center
Manish Gupta , IBM Thomas J. Watson Research Center
Derek Lieber , IBM Thomas J. Watson Research Center
Jose E. Moreira , IBM Thomas J. Watson Research Center
Karin Strauss , IBM Thomas J. Watson Research Center
Henry S. Warren Jr , IBM Thomas J. Watson Research Center
pp. 0311

Author Index (PDF)

pp. 0323
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