The Community for Technology Leaders
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2002)
Boston, Massachusettes
Feb. 2, 2002 to Feb. 6, 2002
ISBN: 0-7695-1525-8
pp: 0311
Calin Cascaval , IBM Thomas J. Watson Research Center
Jose G. Castanos , IBM Thomas J. Watson Research Center
Luis Ceze , IBM Thomas J. Watson Research Center
Monty Denneau , IBM Thomas J. Watson Research Center
Manish Gupta , IBM Thomas J. Watson Research Center
Derek Lieber , IBM Thomas J. Watson Research Center
Jose E. Moreira , IBM Thomas J. Watson Research Center
Karin Strauss , IBM Thomas J. Watson Research Center
Henry S. Warren Jr , IBM Thomas J. Watson Research Center
ABSTRACT
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip SMP system with multiple threads of execution, embedded memory, and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper we describe the Cyclops architecture and evaluate two of its new hardware features: memory hierarchy with flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40\,GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high performance systems.
INDEX TERMS
CITATION
Calin Cascaval, Jose G. Castanos, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, Jose E. Moreira, Karin Strauss, Henry S. Warren Jr, "Evaluation of a Multithreaded Architecture for Cellular Computing", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 0311, 2002, doi:10.1109/HPCA.2002.995720
158 ms
(Ver 3.3 (11022016))