Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling
Proceedings Eighth International Symposium on High Performance Computer Architecture (2002)
Feb. 2, 2002 to Feb. 6, 2002
Greg Semeraro , University of Rochester
Grigorios Magklis , University of Rochester
Rajeev Balasubramonian , University of Rochester
David H. Albonesi , University of Rochester
Sandhya Dwarkadas , University of Rochester
Michael L. Scott , University of Rochester
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor, in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequency scaling can be performed. Boundaries between domains are chosen to exploit existing queues, thereby minimizing inter-domain synchronization costs. We propose four clock domains, corresponding to the front end (including L1 instruction cache), integer units, floating point units, and load-store units (including L1 data cache and L2 cache). We evaluate this design using a simulation infrastructure based on SimpleScalar and Wattch. In an attempt to quantify potential energy savings independent of any particular on-line control strategy, we use off-line analysis of traces from a single-speed run of each of our benchmark applications to identify profitable reconfiguration points for a subsequent dynamic scaling run. Dynamic runs incorporate a detailed model of inter-domain synchronization delays, with latencies for intra-domain scaling similar to the whole-chip scaling latencies of Intel XScale and Transmeta LongRun technologies. Using applications from the MediaBench, Olden, and SPEC2000 benchmark suites, we obtain an average energy-delay product improvement of 20% with MCD compared to a modest 3% savings from voltage scaling a single clock and voltage system.
Multiple Clock Domain, Dynamic Voltage and Frequency Scaling, Off-Line Analysis Tool, Low Power, Dynamic Reconfiguration Algorithm
G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas and M. L. Scott, "Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling," Proceedings Eighth International Symposium on High Performance Computer Architecture(HPCA), Boston, Massachusettes, 2002, pp. 0029.