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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2001)
Nuevo Leone, Mexico
Jan. 20, 2001 to Jan. 24, 2001
ISBN: 0-7695-1019-1
pp: 0159
V. Delaluz , Pennsylvania State University
M. Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
A. Sivasubramaniam , Pennsylvania State University
and M.J. Irwin , Pennsylvania State University
ABSTRACT
Abstract: While there have been several studies and proposals for energy conservation for CPUs and peripherals, energy optimization techniques for selective operating mode control of DRAMs have not been fully explored. It has been shown that as much as 90% of overall system energy (excluding I/O) is consumed by the DRAM modules, serving as a good candidate for energy optimizations. Further, DRAM technology has also matured to provide several low energy operating modes (power modes), making it an opportunistic moment to conduct studies exploring the potential benefits of mode control techniques. This paper conducts an in-depth investigation of software and hardware techniques to avail of the DRAM mode control capabilities at a module granularity for energy savings.
INDEX TERMS
Memory Architecture, Low Power, Low Power Compilation, Software-Directed Energy Management
CITATION
V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M.J. Irwin, "DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 0159, 2001, doi:10.1109/HPCA.2001.903260
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