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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2001)
Nuevo Leone, Mexico
Jan. 20, 2001 to Jan. 24, 2001
ISBN: 0-7695-1019-1
pp: 0027
Pierre Michaud , IRISA/INRIA
André Seznec , IRISA/INRIA
ABSTRACT
Abstract: The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue buffer. Determining which instructions from the issue buffer can be launched to the execution units is a time- critical operation which complexity increases with the issue buffer size. We propose to relieve the issue stage by reordering instructions before they enter the issue buffer. This study introduces the general principle of data-flow prescheduling. Then we describe a possible implementation. Our preliminary results show that data-flow prescheduling makes it possible to enlarge the effective instruction window while keeping the issue buffer small.
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CITATION
Pierre Michaud, André Seznec, "Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 0027, 2001, doi:10.1109/HPCA.2001.903249
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