The Community for Technology Leaders
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2001)
Nuevo Leone, Mexico
Jan. 20, 2001 to Jan. 24, 2001
ISBN: 0-7695-1019-1
pp: 0005
Hsien-Hsin S. Lee , University of Michigan
Mikhail Smelyanskiy , University of Michigan
Gary S. Tyson , University of Michigan
Chris J. Newburn , Intel Corporation
ABSTRACT
Abstract: As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack regions. Each of these designs can improve performance by constructing two separate structures which can be probed in parallel while reducing contention. In this paper, we propose a new memory organization that partitions data references into stack and non-stack regions. Non-stack references are routed to a conventional cache. Stack references, on the other hand, are shown to have several characteristics that can be leveraged to improve performance using a less conventional storage organization. This paper enumerates those characteristics and proposes a new microarchitectural feature, the stack value file (SVF), which exploits them to improve instruction-level parallelism, reduce stack access latencies, reduce demand on the first-level cache, and reduce data bus traffic. Our results show that the SVF can improve execution performance by 29 to 65% while reducing overhead traffic for the stack region by many orders of magnitude over cache structures of the same size.
INDEX TERMS
CITATION
Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Gary S. Tyson, Chris J. Newburn, "Stack Value File: Custom Microarchitecture for the Stack", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 0005, 2001, doi:10.1109/HPCA.2001.903247
98 ms
(Ver 3.3 (11022016))