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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2000)
Toulouse, France
Jan. 8, 2000 to Jan. 12, 2000
ISBN: 0-7695-0550-3
pp: 168
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor and interprocessor communication may further compromise the scalability of these primitives. Ideally, synchronization primitives should provide high performance under both high and low contention without requiring substantial programmer effort and software support. QOLB has been shown to offer substantial speedups and to outperform other synchronization primitives consistently [17], but at the cost of software support and protocol complexity. This paper proposes the use of speculation and delays to implement a purely hardware-based queuing mechanism called Implicit QOLB. Making use of the pervasiveness of the Load-Linked/Store-Conditional primitives, we present a series of hardware mechanisms to optimize performance for sharing patterns exhibited by locks and associated data. The mechanisms do not require any change to existing software or instruction sets. IQOLB sits alongside the cache-coherence protocol and guides the decisions the protocol makes with respect to lock (and associated data) transfers. Preliminary evaluations indicate that IQOLB may perform as well as, if not better than, QOLB without the additional software and protocol complexity.
Synchronization, Speculation, Delays, QOLB, Implicit QOLB, tear-off, shared-memory, multiprocessors, Lock Prediction
Alain Kagi, Ravi Rajwar, James R. Goodman, "Improving the Throughput of Synchronization by Insertion of Delays", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 168, 2000, doi:10.1109/HPCA.2000.824348
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