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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2000)
Toulouse, France
Jan. 8, 2000 to Jan. 12, 2000
ISBN: 0-7695-0550-3
pp: 133
Antonio Gonzalez , Universitat Politecnica de Catalunya
Ramon Canal , Universitat Politecnica de Catalunya
Joan Manuel Parcerisa , Universitat Politecnica de Catalunya
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster microarchitecture with a naive code partitioning approach: integer instructions are allocated to one cluster and floating-point instructions to the other. This partitioning scheme is simple and results in no communications between the two clusters (just through memory) but it is in general far from optimal because the workload is not evenly distributed most of the time. In fact, when the processor is running integer programs, the workload is extremely unbalanced since the FP cluster is not used at all. In this work we investigate run-time mechanisms that dynamically distribute the instructions of a program among these two clusters. By optimizing the trade-off between inter-cluster communication penalty and workload balance, the proposed schemes can achieve an average speed-up of 36% for the SpecInt95 benchmark suite.
Clustered microarchitectures, dynamic code partitioning, steering logic, dynamically scheduled processors
Antonio Gonzalez, Ramon Canal, Joan Manuel Parcerisa, "Dynamic Cluster Assignment Mechanisms", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 133, 2000, doi:10.1109/HPCA.2000.824345
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