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2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2000)
Toulouse, France
Jan. 8, 2000 to Jan. 12, 2000
ISBN: 0-7695-0550-3
pp: 109
James Burns , TRW and University of Southern California
Jean-Luc Gaudiot , University of Southern California
ABSTRACT
Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing micro-architecture with relatively low overhead, this additional chip area could be used for other resources such as more functional units, larger caches or better branch predictors. How large is the SMT overhead, and at what point does SMT no longer pay off compared to adding other architecture features? This paper evaluates the silicon overhead of SMT by performing a transistor/interconnect level analysis of the layout. We discuss micro-architecture issues that impact SMT implementations, and show how the Instruction Set Architecture (ISA) and micro-architecture can have a large effect on the SMT overhead and performance. Results show that SMT yields large performance gains with small to moderate area overhead.
INDEX TERMS
Simultaneous Multi-Threading (SMT)
CITATION
James Burns, Jean-Luc Gaudiot, "Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 109, 2000, doi:10.1109/HPCA.2000.824343
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