The Community for Technology Leaders
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2000)
Toulouse, France
Jan. 8, 2000 to Jan. 12, 2000
ISBN: 0-7695-0550-3
pp: 61
Adi Yoaz , Intel Corporation
Ronny Ronen , Intel Corporation
Lihu Rappoport , Intel Corporation
Yoav Almog , Intel Corporation
Stephan Jourdan , Intel Corporation
Mattan Erez , Intel Corporation
ABSTRACT
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing the same bandwidth. The improved hit rate is achieved by having the XBC a nearly redundant free structure. The basic unit recorded in the XBC is the extended block (XB), which is a multiple-entry single-exit instruction block. A XB is a sequence of instructions ending on a conditional or an indirect branch. Unconditional direct jumps do not end a XB. In order to enable multiple entry points per XB, the XB index is derived from the IP of its ending instruction. Instructions within the XB are recorded in reverse order, enabling easy extension of XBs. The multiple entry-points remove most of the redundancy. Since there is at most one conditional branch per XB, we can fetch up to n XBs per cycle by predicting n branches. The multiple fetch enables the XBC to match the TC bandwidth.
INDEX TERMS
Front-end, instruction cache, trace cache, fetch bandwidth
CITATION
Adi Yoaz, Ronny Ronen, Lihu Rappoport, Yoav Almog, Stephan Jourdan, Mattan Erez, "eXtended Block Cache", 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), vol. 00, no. , pp. 61, 2000, doi:10.1109/HPCA.2000.824339
99 ms
(Ver 3.3 (11022016))